From patchwork Wed Sep 7 10:50:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 666961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sThMJ5Wdwz9s65 for ; Wed, 7 Sep 2016 21:39:24 +1000 (AEST) Received: from localhost ([::1]:39765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhbCL-0004aX-7m for incoming@patchwork.ozlabs.org; Wed, 07 Sep 2016 07:39:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39128) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhaRE-00086S-Ja for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhaRA-0000rs-2y for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:50:39 -0400 Received: from 8.mo173.mail-out.ovh.net ([46.105.46.122]:41669) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhaR9-0000rP-Ep for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:50:35 -0400 Received: from player711.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 5F3FE100C744 for ; Wed, 7 Sep 2016 12:50:33 +0200 (CEST) Received: from hermes.kaod.org (LFbn-1-2234-107.w90-76.abo.wanadoo.fr [90.76.55.107]) (Authenticated sender: clg@kaod.org) by player711.ha.ovh.net (Postfix) with ESMTPSA id BA0363800D9; Wed, 7 Sep 2016 12:50:25 +0200 (CEST) To: Mark Cave-Ayland , David Gibson References: <1466545735-2555-2-git-send-email-clg@kaod.org> <20160622024622.GK17957@voom.fritz.box> <20160623055002.GC17152@voom.fritz.box> <0578ae08-dd95-d517-318e-61b06148321a@redhat.com> <96938c4d-4786-6de0-ed45-9598beb28268@kaod.org> <01b2c7ef-ec04-caba-6ccc-96c77c98f98b@ilande.co.uk> <20160906001640.GA2900@voom.fritz.box> <050980a0-52cc-24ee-1416-d8c8edf959bf@ilande.co.uk> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <9eb184de-1c1b-7a8b-3dcb-edfe3143f9b4@kaod.org> Date: Wed, 7 Sep 2016 12:50:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <050980a0-52cc-24ee-1416-d8c8edf959bf@ilande.co.uk> X-Ovh-Tracer-Id: 17363628364151425905 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeluddriedugdeftdculddtuddrfeeltddrtddtmdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 46.105.46.122 Subject: Re: [Qemu-devel] [PATCH v2 01/10] ppc: Fix rfi/rfid/hrfi/... emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Alexander Graf Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On 09/06/2016 09:07 AM, Mark Cave-Ayland wrote: > On 06/09/16 01:16, David Gibson wrote: > >> On Mon, Sep 05, 2016 at 09:51:09PM +0100, Mark Cave-Ayland wrote: >>> On 05/09/16 21:30, Cédric Le Goater wrote: >>> >>>>> Shall we disable rfi now for QEMU 2.8 ? Cédric, could you maybe send a >>>>> patch with that hunk again? >>>> >>>> Sure. I have kept it in a warm place here : >>>> >>>> https://github.com/legoater/qemu/commit/492a631e4e817863be312c1a34957cd8d679a56c >>>> >>>> Mark, is openbios at the right level now ? I have lost track of the >>>> recent changes. >>> >>> The following patch is already in the current OpenBIOS binaries: >>> https://github.com/openbios/openbios/commit/b747b6acc272f6ab839728193042455c9b36e26a. >>> Is that the one you're looking for? >> >> Right, the relevant question is whether the updated openbios is in the >> qemu submodule and canned binary. > > Yes, it was included in last merge for 2.7. make check-qtest-ppc now runs fine with original patch : https://github.com/legoater/qemu/commit/492a631e4e817863be312c1a34957cd8d679a56c but we could also just remove the rfi instruction from the instruction set of the processors not supporting it. This is where it gets complicated :) I suppose the impact is on 60x, 75x, 74xx, embedded (all the 32bits) but not the 64bits : POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) POWERPC_FAMILY(970)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) This is a bit broader than Ben's patch which used PPC_SEGMENT_64B. it's basically !PPC_64B which includes the e5500. If so, here is a proposal below adding a new PPC_RFI in the "PowerPC Instructions types definitions" enum for that purpose. Not much bits left there. Thanks, C. From: Cédric Le Goater Subject: [PATCH] ppc: enable rfi support for 32bits CPUs only Date: Wed, 07 Sep 2016 11:55:43 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new PPC_RFI bit in the PowerPC Instructions types definitions for this purpose and update the insns_flags of the target CPUs. Signed-off-by: Cédric Le Goater --- target-ppc/cpu.h | 5 +- target-ppc/translate.c | 2 target-ppc/translate_init.c | 92 ++++++++++++++++++++++---------------------- 3 files changed, 51 insertions(+), 48 deletions(-) Index: qemu-dgibson-for-2.8.git/target-ppc/translate.c =================================================================== --- qemu-dgibson-for-2.8.git.orig/target-ppc/translate.c +++ qemu-dgibson-for-2.8.git/target-ppc/translate.c @@ -6297,7 +6297,7 @@ GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x0 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), -GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), +GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_RFI), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), Index: qemu-dgibson-for-2.8.git/target-ppc/cpu.h =================================================================== --- qemu-dgibson-for-2.8.git.orig/target-ppc/cpu.h +++ qemu-dgibson-for-2.8.git/target-ppc/cpu.h @@ -1997,6 +1997,9 @@ enum { /* SLB management */ PPC_SLBI = 0x0000400000000000ULL, + /* rfi support */ + PPC_RFI = 0x0000800000000000ULL, + /* Embedded PowerPC dedicated instructions */ PPC_WRTEE = 0x0001000000000000ULL, /* PowerPC 40x exception model */ @@ -2047,7 +2050,7 @@ enum { | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ - | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ + | PPC_SLBI | PPC_RFI | PPC_WRTEE | PPC_40x_EXCP \ | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ Index: qemu-dgibson-for-2.8.git/target-ppc/translate_init.c =================================================================== --- qemu-dgibson-for-2.8.git.orig/target-ppc/translate_init.c +++ qemu-dgibson-for-2.8.git/target-ppc/translate_init.c @@ -3325,7 +3325,7 @@ POWERPC_FAMILY(401)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << MSR_KEY) | (1ull << MSR_POW) | (1ull << MSR_CE) | @@ -3380,7 +3380,7 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << 20) | (1ull << MSR_KEY) | (1ull << MSR_POW) | @@ -3432,7 +3432,7 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << 20) | (1ull << MSR_KEY) | (1ull << MSR_POW) | @@ -3491,7 +3491,7 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << 20) | (1ull << MSR_KEY) | (1ull << MSR_POW) | @@ -3541,7 +3541,7 @@ POWERPC_FAMILY(403)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_ILE) | @@ -3608,7 +3608,7 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_ILE) | @@ -3674,7 +3674,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, voi PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; + PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -3775,7 +3775,7 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -3858,7 +3858,7 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -3941,7 +3941,7 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -4042,7 +4042,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, v PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -4079,7 +4079,7 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass * PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_MFTB | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->insns_flags2 = PPC2_FP_CVT_S64; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | @@ -4187,7 +4187,7 @@ POWERPC_FAMILY(460)(ObjectClass *oc, voi PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -4297,7 +4297,7 @@ POWERPC_FAMILY(460F)(ObjectClass *oc, vo PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; + PPC_440_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_CE) | (1ull << MSR_EE) | @@ -4341,7 +4341,7 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | - PPC_MFTB; + PPC_MFTB | PPC_RFI; pcc->msr_mask = (1ull << MSR_ILE) | (1ull << MSR_EE) | (1ull << MSR_PR) | @@ -4384,7 +4384,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, pcc->check_pow = check_pow_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | - PPC_CACHE_ICBI | PPC_MFTB; + PPC_CACHE_ICBI | PPC_MFTB | PPC_RFI; pcc->msr_mask = (1ull << MSR_ILE) | (1ull << MSR_EE) | (1ull << MSR_PR) | @@ -4461,7 +4461,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_TGPR) | (1ull << MSR_EE) | @@ -4540,7 +4540,7 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, vo PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_TGPR) | (1ull << MSR_ILE) | @@ -4696,7 +4696,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, vo PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | PPC_TLBIVAX | - PPC_BOOKE; + PPC_BOOKE | PPC_RFI; pcc->msr_mask = (1ull << MSR_UCLE) | (1ull << MSR_SPE) | (1ull << MSR_POW) | @@ -4793,7 +4793,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, vo PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_TGPR) | (1ull << MSR_ILE) | @@ -5052,7 +5052,7 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, PPC_WRTEE | PPC_RFDI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | PPC_RFI; pcc->insns_flags2 = PPC2_BOOKE206; pcc->msr_mask = (1ull << MSR_UCLE) | (1ull << MSR_SPE) | @@ -5095,7 +5095,7 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, PPC_WRTEE | PPC_RFDI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | PPC_RFI; pcc->insns_flags2 = PPC2_BOOKE206; pcc->msr_mask = (1ull << MSR_UCLE) | (1ull << MSR_SPE) | @@ -5140,7 +5140,7 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_WAIT | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | PPC_RFI; pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; pcc->msr_mask = (1ull << MSR_GS) | (1ull << MSR_UCLE) | @@ -5290,7 +5290,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, voi PPC_FLOAT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | @@ -5335,7 +5335,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, vo PPC_FLOAT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | @@ -5396,7 +5396,7 @@ POWERPC_FAMILY(602)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_602_SPEC; + PPC_SEGMENT | PPC_602_SPEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VSX) | (1ull << MSR_SA) | (1ull << MSR_POW) | @@ -5465,7 +5465,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_TGPR) | (1ull << MSR_ILE) | @@ -5531,7 +5531,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, vo PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_TGPR) | (1ull << MSR_ILE) | @@ -5591,7 +5591,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -5674,7 +5674,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, vo PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -5744,7 +5744,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -5822,7 +5822,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6023,7 +6023,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, v PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6105,7 +6105,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, v PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6192,7 +6192,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, v PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6279,7 +6279,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, v PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6357,7 +6357,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6443,7 +6443,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, voi PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; + PPC_SEGMENT | PPC_EXTERN | PPC_RFI; pcc->msr_mask = (1ull << MSR_POW) | (1ull << MSR_ILE) | (1ull << MSR_EE) | @@ -6516,7 +6516,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -6600,7 +6600,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -6710,7 +6710,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -6843,7 +6843,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -6979,7 +6979,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -7117,7 +7117,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -7279,7 +7279,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC | PPC_RFI; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) | (1ull << MSR_ILE) | @@ -7416,7 +7416,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, vo PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_MEM_TLBIA | PPC_74xx_TLB | PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; + PPC_ALTIVEC| PPC_RFI; pcc->insns_flags2 = PPC_NONE; pcc->msr_mask = (1ull << MSR_VR) | (1ull << MSR_POW) |