@@ -767,7 +767,7 @@ static int nvme_init(PCIDevice *pci_dev)
pci_conf = pci_dev->config;
pci_conf[PCI_INTERRUPT_PIN] = 1;
- pci_config_set_prog_interface(pci_dev->config, 0x2);
+ pci_set_byte(pci_dev->config + PCI_CLASS_PROG, 0x2);
pci_set_word(pci_dev->config + PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_EXPRESS);
pcie_endpoint_cap_init(&n->parent_obj, 0x80);
@@ -393,7 +393,7 @@ static int xen_platform_initfn(PCIDevice *dev)
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
- pci_config_set_prog_interface(pci_conf, 0);
+ pci_set_byte(pci_conf + PCI_CLASS_PROG, 0);
pci_conf[PCI_INTERRUPT_PIN] = 1;
@@ -88,7 +88,7 @@ static int xen_pv_init(PCIDevice *pci_dev)
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_MEMORY);
- pci_config_set_prog_interface(pci_conf, 0);
+ pci_set_byte(pci_conf + PCI_CLASS_PROG, 0);
pci_conf[PCI_INTERRUPT_PIN] = 1;
@@ -107,7 +107,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
- pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
+ pci_set_byte(dev->config + PCI_CLASS_PROG, AHCI_PROGMODE_MAJOR_REV_1);
dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
@@ -177,7 +177,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
- pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
+ pci_set_byte(pci_conf + PCI_CLASS_PROG, 0x8a); /* legacy ATA mode */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
qemu_register_reset(via_reset, d);
@@ -435,7 +435,7 @@ static int vt82c686b_initfn(PCIDevice *d)
isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d));
pci_conf = d->config;
- pci_config_set_prog_interface(pci_conf, 0x0);
+ pci_set_byte(pci_conf + PCI_CLASS_PROG, 0x0);
wmask = d->wmask;
for (i = 0x00; i < 0xff; i++) {
@@ -1157,7 +1157,7 @@ static int gt64120_pci_init(PCIDevice *d)
pci_set_word(d->config + PCI_COMMAND, 0);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
- pci_config_set_prog_interface(d->config, 0);
+ pci_set_byte(d->config + PCI_CLASS_PROG, 0);
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
@@ -71,7 +71,7 @@ static int i82801b11_bridge_initfn(PCIDevice *d)
if (rc < 0) {
goto err_bridge;
}
- pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB);
+ pci_set_byte(d->config + PCI_CLASS_PROG, PCI_CLASS_BRIDGE_PCI_INF_SUB);
return 0;
err_bridge:
@@ -712,7 +712,7 @@ static int bonito_initfn(PCIDevice *dev)
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
- pci_config_set_prog_interface(dev->config, 0x00);
+ pci_set_byte(dev->config + PCI_CLASS_PROG, 0x00);
/* set the north bridge register mapping */
memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
@@ -462,12 +462,6 @@ pci_get_quad(const uint8_t *config)
}
static inline void
-pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
-{
- pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
-}
-
-static inline void
pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
{
pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
See also commit 'pci: remove pci_config_set_vendor_id'. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> --- hw/block/nvme.c | 2 +- hw/i386/xen/xen_platform.c | 2 +- hw/i386/xen/xen_pvdevice.c | 2 +- hw/ide/ich.c | 2 +- hw/ide/via.c | 2 +- hw/isa/vt82c686.c | 2 +- hw/mips/gt64xxx_pci.c | 2 +- hw/pci-bridge/i82801b11.c | 2 +- hw/pci-host/bonito.c | 2 +- include/hw/pci/pci.h | 6 ------ 10 files changed, 9 insertions(+), 15 deletions(-)