@@ -58,12 +58,20 @@ void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
}
uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
- uint32_t limit, uint32_t len)
+ uint32_t len)
{
+ uint32_t limit = pci_config_size(pci_dev);
uint32_t ret;
assert(len <= 4);
- ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
+
+ if (limit <= addr) {
+ /* conventional pci device can be behind pcie-to-pci bridge.
+ 256 <= addr < 4K has no effects. */
+ ret = ~0x0;
+ } else {
+ ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
+ }
trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn),
PCI_FUNC(pci_dev->devfn), addr, ret);
@@ -95,8 +103,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return ~0x0;
}
- val = pci_host_config_read_common(pci_dev, config_addr,
- PCI_CONFIG_SPACE_SIZE, len);
+ val = pci_host_config_read_common(pci_dev, config_addr, len);
PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
__func__, pci_dev->name, config_addr, val, len);
@@ -62,19 +62,12 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
- uint32_t limit;
if (!pci_dev) {
return ~0x0;
}
addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
- limit = pci_config_size(pci_dev);
- if (limit <= addr) {
- /* conventional pci device can be behind pcie-to-pci bridge.
- 256 <= addr < 4K has no effects. */
- return ~0x0;
- }
- return pci_host_config_read_common(pci_dev, addr, limit, len);
+ return pci_host_config_read_common(pci_dev, addr, len);
}
static const MemoryRegionOps pcie_mmcfg_ops = {
@@ -105,8 +105,7 @@ static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid,
return;
}
- val = pci_host_config_read_common(pci_dev, addr,
- pci_config_size(pci_dev), size);
+ val = pci_host_config_read_common(pci_dev, addr, size);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
rtas_st(rets, 1, val);
@@ -60,7 +60,7 @@ typedef struct PCIHostBridgeClass {
void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
uint32_t limit, uint32_t val, uint32_t len);
uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
- uint32_t limit, uint32_t len);
+ uint32_t len);
void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
Since the limit parameter is always set to the size of pci device's configuration space, and we can determine the size from the type of pci device. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> --- hw/pci/pci_host.c | 15 +++++++++++---- hw/pci/pcie_host.c | 9 +-------- hw/ppc/spapr_pci.c | 3 +-- include/hw/pci/pci_host.h | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-)