From patchwork Thu Oct 16 08:56:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 400228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A35D31400D2 for ; Thu, 16 Oct 2014 19:58:07 +1100 (AEDT) Received: from localhost ([::1]:49286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xegsn-0002m8-JN for incoming@patchwork.ozlabs.org; Thu, 16 Oct 2014 04:58:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xegs2-0001Y6-J3 for qemu-devel@nongnu.org; Thu, 16 Oct 2014 04:57:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xegrq-0006Uv-VN for qemu-devel@nongnu.org; Thu, 16 Oct 2014 04:57:18 -0400 Received: from smtp.ispras.ru ([83.149.199.79]:49282) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xegrq-0006UI-Ok for qemu-devel@nongnu.org; Thu, 16 Oct 2014 04:57:06 -0400 Received: from bulbul.intra.ispras.ru (unknown [83.149.199.91]) by smtp.ispras.ru (Postfix) with ESMTP id 17998224C2; Thu, 16 Oct 2014 12:57:06 +0400 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 16 Oct 2014 12:56:52 +0400 Message-Id: <8ed6bfbaa332faf6be22867054977e46b39a5b7c.1413286807.git.batuzovk@ispras.ru> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: <87k3571pb5.fsf@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 83.149.199.79 Cc: Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Kirill Batuzov Subject: [Qemu-devel] [PATCH RFC 5/7] target-arm: support access to 128-bit guest registers as globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To support 128-bit guest registers as globals we need to do two things: 1) create corresponding globals, 2) add sync_temp/discard to code that access these registers as memory locations. Note that the second part is not complete in this RFC yet and mixing NEON with VFP code can result in miscompile. Signed-off-by: Kirill Batuzov --- target-arm/translate.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 8a2994f..22855d8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -64,6 +64,7 @@ TCGv_ptr cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; +static TCGv_v128 cpu_Q[16]; static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; static TCGv_i64 cpu_exclusive_addr; static TCGv_i64 cpu_exclusive_val; @@ -78,10 +79,14 @@ static TCGv_i64 cpu_F0d, cpu_F1d; #include "exec/gen-icount.h" -static const char *regnames[] = +static const char *regnames_r[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; +static const char *regnames_q[] = + { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", + "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" }; + /* initialize TCG globals. */ void arm_translate_init(void) { @@ -92,7 +97,12 @@ void arm_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, regs[i]), - regnames[i]); + regnames_r[i]); + } + for (i = 0; i < 16; i++) { + cpu_Q[i] = tcg_global_mem_new_v128(TCG_AREG0, + offsetof(CPUARMState, vfp.regs[2 * i]), + regnames_q[i]); } cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF"); cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF"); @@ -1237,23 +1247,27 @@ neon_reg_offset (int reg, int n) static TCGv_i32 neon_load_reg(int reg, int pass) { TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_sync_temp_v128(cpu_Q[reg >> 1]); tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); return tmp; } static void neon_store_reg(int reg, int pass, TCGv_i32 var) { + tcg_gen_discard_v128(cpu_Q[reg >> 1]); tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); tcg_temp_free_i32(var); } static inline void neon_load_reg64(TCGv_i64 var, int reg) { + tcg_gen_sync_temp_v128(cpu_Q[reg >> 1]); tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); } static inline void neon_store_reg64(TCGv_i64 var, int reg) { + tcg_gen_discard_v128(cpu_Q[reg >> 1]); tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); }