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Thu, 12 May 2016 22:49:30 +0000 Received: from 172-16-1-203.xilinx.com ([172.16.1.203]:57358 helo=xsj-tvapsmtp02.xilinx.com) by xsj-tvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1b0zQA-0007gd-Aj; Thu, 12 May 2016 15:49:30 -0700 Received: from [127.0.0.1] (port=37966 helo=tsj-smtp-dlp1.xlnx.xilinx.com) by xsj-tvapsmtp02.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1b0zQA-0005fN-7a; Thu, 12 May 2016 15:49:30 -0700 Received: from xsj-tvapsmtp02 (smtptest.xilinx.com [172.16.1.203]) by tsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u4CMhE62016009; Thu, 12 May 2016 15:43:14 -0700 Received: from [172.19.74.182] (port=36118 helo=xsjalistai50.xlnx.xilinx.com) by xsj-tvapsmtp02 with esmtp (Exim 4.63) (envelope-from ) id 1b0zQ9-0005fJ-BK; Thu, 12 May 2016 15:49:29 -0700 From: Alistair Francis To: , Date: Thu, 12 May 2016 15:46:03 -0700 Message-ID: <8eb128d39abd89ae6a0d74e965c262650d3bf863.1463093051.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22316.005 X-TM-AS-Result: No--9.877-7.0-31-10 X-imss-scan-details: No--9.877-7.0-31-10 X-TMASE-MatchedRID: Qb48SpHNPW7/uyguzMmOKBWCVBr+Ay98tZN20SHV1TSneP2LcHykgd/9 N6lK9KH6rLrdQysupgx7XrDFT6+EKZnghuhFDtTnS3OTftLNfg2K6IJmwLQESBwKSCi0KXuE3oz JRX7b4NmOACjEIVDcsTEzpCEHqTDO7PE1ojYEvaH/hOhZ6EJFBQRryDXHx6oXv+26ZYWzwkKZCv kc8xHjBTdSigtTkRec747pJRuETOn2d45/2oc10J4CIKY/Hg3AGdQnQSTrKGPEQdG7H66TyH4gK q42LRYk9ujaIwO6gEKSfxQoB0VJp4gNs9b6tsosTZ99HTF4ig9+3BndfXUhXQ== X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.96; 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PCL:0; RULEID:(601004)(2401047)(13017025)(13015025)(13023025)(8121501046)(5005006)(13024025)(13018025)(3002001)(10201501046)(6055026); SRVR:CY1NAM02HT169; BCL:0; PCL:0; RULEID:; SRVR:CY1NAM02HT169; X-Forefront-PRVS: 0940A19703 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2016 22:49:30.8522 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT169 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.70 Subject: [Qemu-devel] [PATCH v6 05/13] register: QOMify X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, alex.bennee@linaro.org, afaerber@suse.de, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Peter Crosthwaite QOMify registers as a child of TYPE_DEVICE. This allows registers to define GPIOs. Define an init helper that will do QOM initialisation. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis Reviewed-by: KONRAD Frederic --- V5: - Convert to using only one memory region hw/core/register.c | 23 +++++++++++++++++++++++ include/hw/register.h | 15 +++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/hw/core/register.c b/hw/core/register.c index 25196e6..c5a2c78 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -148,6 +148,17 @@ void register_reset(RegisterInfo *reg) register_write_val(reg, reg->access->reset); } +void register_init(RegisterInfo *reg) +{ + assert(reg); + + if (!reg->data || !reg->access) { + return; + } + + object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER); +} + static inline void register_write_memory(void *opaque, hwaddr addr, uint64_t value, unsigned size, bool be) { @@ -219,3 +230,15 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size) { return register_read_memory(opaque, addr, size, false); } + +static const TypeInfo register_info = { + .name = TYPE_REGISTER, + .parent = TYPE_DEVICE, +}; + +static void register_register_types(void) +{ + type_register_static(®ister_info); +} + +type_init(register_register_types) diff --git a/include/hw/register.h b/include/hw/register.h index e0aac91..eedd578 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -11,6 +11,7 @@ #ifndef REGISTER_H #define REGISTER_H +#include "hw/qdev-core.h" #include "exec/memory.h" typedef struct RegisterInfo RegisterInfo; @@ -74,6 +75,9 @@ struct RegisterAccessInfo { */ struct RegisterInfo { + /* */ + DeviceState parent_obj; + /* */ void *data; int data_size; @@ -83,6 +87,9 @@ struct RegisterInfo { void *opaque; }; +#define TYPE_REGISTER "qemu,register" +#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER) + /** * This structure is used to group all of the individual registers which are * modeled using the RegisterInfo strucutre. @@ -132,6 +139,14 @@ uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug); void register_reset(RegisterInfo *reg); /** + * Initialize a register. GPIO's are setup as IOs to the specified device. + * Fast paths for eligible registers are enabled. + * @reg: Register to initialize + */ + +void register_init(RegisterInfo *reg); + +/** * Memory API MMIO write handler that will write to a Register API register. * _be for big endian variant and _le for little endian. * @opaque: RegisterInfo to write to