From patchwork Thu May 28 05:38:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 478101 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1YxqX0-0004MQ-T1 for mharc-qemu-devel@gnu.org; Thu, 28 May 2015 01:39:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqWy-0004I1-Lz for qemu-devel@nongnu.org; Thu, 28 May 2015 01:39:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxqWv-000749-2G for qemu-devel@nongnu.org; Thu, 28 May 2015 01:39:00 -0400 Received: from mail-pd0-x233.google.com ([2607:f8b0:400e:c02::233]:34669) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqWu-000743-Re for qemu-devel@nongnu.org; Thu, 28 May 2015 01:38:57 -0400 Received: by pdbki1 with SMTP id ki1so33818589pdb.1 for ; Wed, 27 May 2015 22:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ND4kMX3sgcJXgy0mB+eKRZ9jREyPHMCzlVnDcZaLNao=; b=PsCipyZV4eoOyhIytvuPpwXPUe9bPz/0n1ocmgfDmRG9U8UnuNDsi4vU4XGOOQKRXt zq3uUMf0oOW5CTOwrqaObBfyezVLY6CaeYtigU0uTLVXuN2IWbRpXQLL/nqUXQmInO78 WRNuKkts0KPCrOx4kS2jetinof4MDe/dKizRRifrtSiMSxBkOU+FTMNLbk4EhpVYBlcf 1jOctTwmcjCxCBLyH3lt3Esm2iE7FLTlJ39grOwxGhqHfkBrT5KZX+X/MC8ffyP9h6Fw nPqRgcYORmkeBZ6A4U+HX2MTpMUrsfSVUGXCVief/K1tRQ52QPzD7IvdvzqeeCKyGNuJ Yi/A== X-Received: by 10.67.4.230 with SMTP id ch6mr2125986pad.137.1432791536199; Wed, 27 May 2015 22:38:56 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ku10sm970992pab.3.2015.05.27.22.38.54 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 27 May 2015 22:38:55 -0700 (PDT) Sender: Alistair Francis From: Alistair Francis To: qemu-devel@nongnu.org, edgar.iglesias@xilinx.com Date: Thu, 28 May 2015 15:38:21 +1000 Message-Id: <8a68f259adf7c57fee36e9d81d7bf84d9ea4001e.1432790821.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::233 Cc: peter.crosthwaite@xilinx.com, rth@twiddle.net, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v2 4/5] target-microblaze: Tidy up the base-vectors property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 May 2015 05:39:01 -0000 Rename the "xlnx.base-vectors" string to "base-vectors" and move the base_vectors variable into the cfg struct. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- target-microblaze/cpu-qom.h | 3 ++- target-microblaze/cpu.c | 4 ++-- target-microblaze/helper.c | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index e08adb9..dd04199 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -56,12 +56,13 @@ typedef struct MicroBlazeCPUClass { typedef struct MicroBlazeCPU { /*< private >*/ CPUState parent_obj; - uint32_t base_vectors; + /*< public >*/ /* Microblaze Configuration Settings */ struct { bool stackprot; + uint32_t base_vectors; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index ead2fcd..aefdd7a 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -120,7 +120,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); - env->sregs[SR_PC] = cpu->base_vectors; + env->sregs[SR_PC] = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ @@ -158,7 +158,7 @@ static const VMStateDescription vmstate_mb_cpu = { }; static Property mb_properties[] = { - DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, false), DEFINE_PROP_END_OF_LIST(), diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 32896f4..69c3252 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -154,7 +154,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: @@ -194,7 +194,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -235,7 +235,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->base_vectors + 0x10; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -254,7 +254,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->base_vectors + 0x18; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; } else env->sregs[SR_PC] = env->btarget; break;