From patchwork Fri May 20 12:39:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 96593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 00928B719D for ; Fri, 20 May 2011 22:41:48 +1000 (EST) Received: from localhost ([::1]:54592 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNP1V-0000pi-8b for incoming@patchwork.ozlabs.org; Fri, 20 May 2011 08:41:45 -0400 Received: from eggs.gnu.org ([140.186.70.92]:44845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNOzr-0006ug-U9 for qemu-devel@nongnu.org; Fri, 20 May 2011 08:40:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QNOzq-0003bf-3I for qemu-devel@nongnu.org; Fri, 20 May 2011 08:40:03 -0400 Received: from smtp.ispras.ru ([83.149.198.202]:55461) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNOzp-0003Xx-LW for qemu-devel@nongnu.org; Fri, 20 May 2011 08:40:02 -0400 Received: from bulbul.intra.ispras.ru (winnie.ispras.ru [83.149.198.236]) by smtp.ispras.ru (Postfix) with ESMTP id 00E875D4119; Fri, 20 May 2011 16:36:09 +0400 (MSD) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Fri, 20 May 2011 16:39:31 +0400 Message-Id: <898222ebb06df066cad8c5286bee65319e46789a.1305889001.git.batuzovk@ispras.ru> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 83.149.198.202 Cc: mj.mccormack@samsung.com, zhur@ispras.ru Subject: [Qemu-devel] [PATCH 4/6] Do constant folding for boolean operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Perform constant folding for AND, OR, XOR operations. Signed-off-by: Kirill Batuzov --- tcg/optimize.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 4073f05..a02d5c1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -38,6 +38,13 @@ typedef enum { TCG_TEMP_ANY } tcg_temp_state; +const int mov_opc[] = { + INDEX_op_mov_i32, +#if TCG_TARGET_REG_BITS == 64 + INDEX_op_mov_i64, +#endif +}; + static int mov_to_movi(int op) { switch (op) { @@ -89,12 +96,18 @@ static int op_bits(int op) case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: return 32; #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: case INDEX_op_add_i64: case INDEX_op_sub_i64: case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: return 64; #endif default: @@ -137,6 +150,24 @@ static TCGArg do_constant_folding_2(int op, TCGArg x, TCGArg y) #endif return x * y; + case INDEX_op_and_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_and_i64: +#endif + return x & y; + + case INDEX_op_or_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_or_i64: +#endif + return x | y; + + case INDEX_op_xor_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_xor_i64: +#endif + return x ^ y; + default: fprintf(stderr, "Unrecognized operation %d in do_constant_folding.\n", op); @@ -237,10 +268,37 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, gen_args += 2; args += 2; break; + case INDEX_op_or_i32: + case INDEX_op_and_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_and_i64: + case INDEX_op_or_i64: +#endif + if (args[1] == args[2]) { + if (args[1] == args[0]) { + args += 3; + gen_opc_buf[op_index] = INDEX_op_nop; + } else { + reset_temp(state, vals, args[0], nb_temps, nb_globals); + if (args[1] >= s->nb_globals) { + state[args[0]] = TCG_TEMP_COPY; + vals[args[0]] = args[1]; + } + gen_opc_buf[op_index] = mov_opc[op_bits(op) / 32 - 1]; + gen_args[0] = args[0]; + gen_args[1] = args[1]; + gen_args += 2; + args += 3; + } + break; + } + /* Proceed with default binary operation handling */ + case INDEX_op_xor_i32: case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_mul_i32: #if TCG_TARGET_REG_BITS == 64 + case INDEX_op_xor_i64: case INDEX_op_add_i64: case INDEX_op_sub_i64: case INDEX_op_mul_i64: