From patchwork Mon Jan 20 00:09:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 312425 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7C7272C00A7 for ; Mon, 20 Jan 2014 11:10:48 +1100 (EST) Received: from localhost ([::1]:48145 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W52Ry-0000P9-5g for incoming@patchwork.ozlabs.org; Sun, 19 Jan 2014 19:10:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W52RA-0000Lq-KQ for qemu-devel@nongnu.org; Sun, 19 Jan 2014 19:10:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W52R3-0003sa-Im for qemu-devel@nongnu.org; Sun, 19 Jan 2014 19:09:56 -0500 Received: from mail-qa0-x233.google.com ([2607:f8b0:400d:c00::233]:54112) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W52R3-0003sS-EH for qemu-devel@nongnu.org; Sun, 19 Jan 2014 19:09:49 -0500 Received: by mail-qa0-f51.google.com with SMTP id f11so5015605qae.24 for ; Sun, 19 Jan 2014 16:09:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=6tym89ROnN3T9kgMTrsRn5BMMgy4DlBgLdjL56OfJIs=; b=DQL/v5+ziQ5UQa1dw3pv+roGYY5RMNBxU3o3Ltl1Iyr9V9Qv+rZYojDMXfJUAYNKxi tENL56h8u7odShwVR8SpNiO/QhNEH4Gqs4nnYgjVmZbFEfsJDvJd0xd400A+E3RICzRl XSDhNwyRSK8MDVyStDhFdoLDVjX8iIx8U78ZTxvPA0eDC+0Ci3nNclKZ5xbC+dJ0u4Vo 1DhuY7DG2jgNYb5TK7fdc9E17X6gAcDc6DatSWGHroLxv/c8KRzPefUsQ5YXKJGd5MNH LSsxPQEx1l5YBZMD1PQM/BQOJgI08+gJz7F5DEEq5cYidQfUDm7HfnTUu7Viu1xEdY9F 3S6w== X-Received: by 10.140.28.134 with SMTP id 6mr21973263qgz.50.1390176589053; Sun, 19 Jan 2014 16:09:49 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id m9sm22820856qaz.8.2014.01.19.16.09.47 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sun, 19 Jan 2014 16:09:48 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Mon, 20 Jan 2014 10:09:45 +1000 Message-Id: <878613f2f12d4162f12629522fd99de8df904856.1390176489.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c00::233 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH arm-midr v3 1/2] ARM: Convert MIDR to a property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the MIDR register to a property. This allows boards to later set a custom MIDR value. This has been done in such a way to maintain compatibility with all existing CPUs and boards Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- I originally added the properties to the cpu->midr variable in a similar method to how Peter Crosthwaite did in his 'Fix Support for ARM CBAR and reset-hivecs' series. V3: Removed the initialisation of the MIDR property from arm_cpu_post_init as it is no longer needed V2: Use dc->props to avoid using qdev_* target-arm/cpu.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 52efd5d..45ad7f0 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -982,6 +982,7 @@ static const ARMCPUInfo arm_cpus[] = { static Property arm_cpu_properties[] = { DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), + DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), DEFINE_PROP_END_OF_LIST() };