From patchwork Thu Oct 4 00:16:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 188966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4223B2C033A for ; Thu, 4 Oct 2012 10:16:49 +1000 (EST) Received: from localhost ([::1]:35453 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ7P-000700-8g for incoming@patchwork.ozlabs.org; Wed, 03 Oct 2012 20:16:47 -0400 Received: from eggs.gnu.org ([208.118.235.92]:49012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ77-0006ow-4Y for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJZ75-0004zg-LG for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:28 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:52787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ75-0004zb-Eb for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:27 -0400 Received: by dadn15 with SMTP id n15so2646926dad.4 for ; Wed, 03 Oct 2012 17:16:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=ck4LfXQXUFlqoYN6uzOFZYHKJU9P0/4KpJrABeQkrlM=; b=Kj+8lsmW4ecHN1ejH6mF08rdh8nE+TSoUdaPSQ+sj/XX8yOinAAe0gd0TqdU0EwtCT GndUV++QrjBAzuoBD2fIpQr9TH1/lWh4xKjIK+08snAI2WQ28zXJHfl4ZUZ07cETwxme TJy5hiJ4IZw70rzNFyw2xeYJvnCmUTvrpK8zxn1IMae5Qz81HNAHtPVSNBc8aYfGrFLR G5wzB0rM7JBsCD8k7xWsed80cqMaVSWWBz84N5e/ImwA5tHe7BRO7kCZxNuiwnNrdmeF t3j2y7hNqSJEZN6vGQAg9pPY/2e1CRBM2EiGieGFZa9ary4W7kcJIAHzmzACV1CzcOZf xzUg== Received: by 10.66.78.6 with SMTP id x6mr8811235paw.41.1349309786243; Wed, 03 Oct 2012 17:16:26 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id ko8sm3351519pbc.40.2012.10.03.17.16.23 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 17:16:25 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org, edgar.iglesias@gmail.com Date: Thu, 4 Oct 2012 10:16:12 +1000 Message-Id: <85f8fdbc83b3a0e1d1aaf7cbc79bf4a79df0851c.1349308835.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQlKtaxCGMrIj2IjAnwNqu9hzsvBE56aWdV9EqlW/yusYz4aLTYyAWKw0ZxLiCvX3zAmvvpw X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: linnj@xilinx.com, "Peter A. G. Crosthwaite" , john.williams@petalogix.com Subject: [Qemu-devel] [PATCH v2 2/4] zynq_slcr: Add links to the CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite The SLCR needs to be able to reset the CPUs, so link the CPUs to the slcr. Signed-off-by: Peter A. G. Crosthwaite --- hw/xilinx_zynq.c | 11 +++++++++++ hw/zynq_slcr.c | 9 +++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 22a2bc5..fc81521 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -100,6 +100,10 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, } irqp = arm_pic_init_cpu(cpus[n]); cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; + /* FIXME: handle this somewhere central */ + object_property_add_child(container_get(qdev_get_machine(), + "/unattached"), g_strdup_printf("cpu[%d]", n), + OBJECT(cpus[n]), NULL); } /* max 2GB ram */ @@ -128,6 +132,13 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, dev = qdev_create(NULL, "xilinx,zynq_slcr"); qdev_init_nofail(dev); + Error *errp = NULL; + object_property_set_link(OBJECT(dev), OBJECT(cpus[0]), "cpu0", &errp); + assert_no_error(errp); + if (smp_cpus > 1) { + object_property_set_link(OBJECT(dev), OBJECT(cpus[1]), "cpu1", NULL); + assert_no_error(errp); + } sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000); dev = qdev_create(NULL, "a9mpcore_priv"); diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c index 4f97575..468fb0e 100644 --- a/hw/zynq_slcr.c +++ b/hw/zynq_slcr.c @@ -19,6 +19,8 @@ #include "sysbus.h" #include "sysemu.h" +#define NUM_CPUS 2 + #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG #define DB_PRINT(...) do { \ fprintf(stderr, ": %s: ", __func__); \ @@ -118,6 +120,8 @@ typedef struct { SysBusDevice busdev; MemoryRegion iomem; + ARMCPU *cpus[NUM_CPUS]; + union { struct { uint16_t scl; @@ -496,6 +500,11 @@ static int zynq_slcr_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000); sysbus_init_mmio(dev, &s->iomem); + object_property_add_link(OBJECT(dev), "cpu0", TYPE_ARM_CPU, + (Object **) &s->cpus[0], NULL); + object_property_add_link(OBJECT(dev), "cpu1", TYPE_ARM_CPU, + (Object **) &s->cpus[1], NULL); + return 0; }