From patchwork Mon Aug 5 01:21:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chubb X-Patchwork-Id: 264558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 87A132C0084 for ; Mon, 5 Aug 2013 11:22:02 +1000 (EST) Received: from localhost ([::1]:49027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69Ul-0002jj-7m for incoming@patchwork.ozlabs.org; Sun, 04 Aug 2013 21:21:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69UK-0002VH-Bb for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:21:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V69UB-0003jX-8x for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:21:32 -0400 Received: from lemon.ertos.nicta.com.au ([203.143.174.143]:49205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69UA-0003gF-Rs for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:21:23 -0400 Received: from [2402:1800:4000:2:224:d7ff:feaf:390] (port=59978 helo=Diprotodon.chubb.wattle.id.au) by lemon.ertos.nicta.com.au with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1V69TK-0000yZ-HQ; Mon, 05 Aug 2013 11:20:31 +1000 Date: Mon, 05 Aug 2013 11:21:11 +1000 Message-ID: <84r4e9j5ko.wl%peter.chubb@nicta.com.au> From: Peter Chubb To: Peter Maydell , qemu-devel@nongnu.org User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/23.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Face: GgFg(Z>fx((4\32hvXq<)|jndSniCH~~$D)Ka:P@e@JR1P%Vr}EwUdfwf-4j\rUs#JR{'h# !]])6%Jh~b$VA|ALhnpPiHu[-x~@<"@Iv&|%R)Fq[[, (&Z'O)Q)xCqe1\M[F8#9l8~}#u$S$Rm`S9% \'T@`:&8>Sb*c5d'=eDYI&GF`+t[LfDH="MP5rwOO]w>ALi7'=QJHz&y&C&TE_3j! Organization: NICTA MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 2402:1800:4000:2:224:d7ff:feaf:390 X-SA-Exim-Mail-From: peter.chubb@nicta.com.au X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:56:45 +0000) X-SA-Exim-Scanned: Yes (on lemon.ertos.nicta.com.au) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 203.143.174.143 Subject: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reads to unassigned memory now return non-zero (since patch 9b8c69243585). This breaks guests runnong on i.MX31 that use the cache controller --- they poll forever waiting for the L2CC cache invalidate regsiter to be zero. This patch adds in an L2 cache controller. It's not quite right --- it reuses the PL2x0 implementation that is already in QEMU. The differences however are minor --- a different ID, a different initial value for the aux control register (because Freescale have used some of the reserved bits), and the pl2x0 implements registers that are not present in the Freescale cache controller. Signed-off-by: Peter Chubb --- Dr Peter Chubb peter.chubb AT nicta.com.au http://www.ssrg.nicta.com.au Software Systems Research Group/NICTA diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index bd6c05c..018fc81 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -33,6 +33,7 @@ * 0x1fffc000-0x1fffffff RAM EMULATED * 0x20000000-0x2fffffff Reserved IGNORED * 0x30000000-0x7fffffff I.MX31 Internal Register Space + * 0x30000000-0x30000fff L2 Cache Controller PARTIALLY EMULATED * 0x43f00000 IO_AREA0 * 0x43f90000 UART1 EMULATED * 0x43f94000 UART2 EMULATED @@ -134,6 +135,15 @@ static void kzm_init(QEMUMachineInitArgs *args) DEVICE_NATIVE_ENDIAN); } + /* + * The i.MX L2CC is almost the same as the PL210 + * except for a different ID (the implementor bits are different) + * and the `reserved' bits in the auxilliary control register + * are implemented. The l2x0 qemu implementation is for a superset + * of the PL210. + */ + sysbus_create_varargs("l2x0", 0x30000000, NULL); + kzm_binfo.ram_size = ram_size; kzm_binfo.kernel_filename = kernel_filename; kzm_binfo.kernel_cmdline = kernel_cmdline;