From patchwork Mon Aug 5 01:27:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chubb X-Patchwork-Id: 264559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1B412C0092 for ; Mon, 5 Aug 2013 11:27:47 +1000 (EST) Received: from localhost ([::1]:50720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69aL-0005Bm-GJ for incoming@patchwork.ozlabs.org; Sun, 04 Aug 2013 21:27:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69a2-0005Ba-PR for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:27:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V69Zy-0005Ym-I1 for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:27:26 -0400 Received: from lemon.ertos.nicta.com.au ([203.143.174.143]:49228) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V69Zx-0005YW-Vs for qemu-devel@nongnu.org; Sun, 04 Aug 2013 21:27:22 -0400 Received: from [2402:1800:4000:2:224:d7ff:feaf:390] (port=59982 helo=Diprotodon.chubb.wattle.id.au) by lemon.ertos.nicta.com.au with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1V69ZC-0000zX-Hw; Mon, 05 Aug 2013 11:26:38 +1000 Date: Mon, 05 Aug 2013 11:27:15 +1000 Message-ID: <84ppttj5ak.wl%peter.chubb@nicta.com.au> From: Peter Chubb To: peter.maydell@linaro.org, qemu-devel@nongnu.org User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/23.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Face: GgFg(Z>fx((4\32hvXq<)|jndSniCH~~$D)Ka:P@e@JR1P%Vr}EwUdfwf-4j\rUs#JR{'h# !]])6%Jh~b$VA|ALhnpPiHu[-x~@<"@Iv&|%R)Fq[[, (&Z'O)Q)xCqe1\M[F8#9l8~}#u$S$Rm`S9% \'T@`:&8>Sb*c5d'=eDYI&GF`+t[LfDH="MP5rwOO]w>ALi7'=QJHz&y&C&TE_3j! Organization: NICTA MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 2402:1800:4000:2:224:d7ff:feaf:390 X-SA-Exim-Mail-From: peter.chubb@nicta.com.au X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:56:45 +0000) X-SA-Exim-Scanned: Yes (on lemon.ertos.nicta.com.au) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 203.143.174.143 Subject: [Qemu-devel] [Patch] ARM: Simplify and fix imx_epit implementation. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When imx_epit.c was last refactored, a common usecase (comparison register zero) broke. This patch fixes that, and simplifies the code yet more. It also fixes a major thinko in the reset path --- the wrong bits in the control register were being cleared. Signed-off-by: Peter Chubb Reviewed-by: Jean-Christophe DUBOIS --- hw/timer/imx_epit.c | 94 +++++++++++++++++++--------------------------------- 1 file changed, 36 insertions(+), 58 deletions(-) -- Dr Peter Chubb peter.chubb AT nicta.com.au http://www.ssrg.nicta.com.au Software Systems Research Group/NICTA Index: qemu/hw/timer/imx_epit.c =================================================================== --- qemu.orig/hw/timer/imx_epit.c 2013-08-02 14:07:06.598276595 +1000 +++ qemu/hw/timer/imx_epit.c 2013-08-02 14:31:28.494031219 +1000 @@ -43,7 +43,7 @@ static char const *imx_epit_reg_name(uin } # define DPRINTF(fmt, args...) \ - do { printf("%s: " fmt , __func__, ##args); } while (0) + do { fprintf(stderr, "%s: " fmt , __func__, ##args); } while (0) #else # define DPRINTF(fmt, args...) do {} while (0) #endif @@ -152,7 +152,7 @@ static void imx_epit_reset(DeviceState * /* * Soft reset doesn't touch some bits; hard reset clears them */ - s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); s->sr = 0; s->lr = TIMER_MAX; s->cmp = 0; @@ -167,7 +167,7 @@ static void imx_epit_reset(DeviceState * ptimer_set_limit(s->timer_reload, TIMER_MAX, 1); if (s->freq && (s->cr & CR_EN)) { /* if the timer is still enabled, restart it */ - ptimer_run(s->timer_reload, 1); + ptimer_run(s->timer_reload, 0); } } @@ -218,17 +218,17 @@ static uint64_t imx_epit_read(void *opaq static void imx_epit_reload_compare_timer(IMXEPITState *s) { - if ((s->cr & CR_OCIEN) && s->cmp) { - /* if the compare feature is on */ + if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { + /* if the compare feature is on and timers are running */ uint32_t tmp = imx_epit_update_count(s); + uint64_t next; if (tmp > s->cmp) { - /* reinit the cmp timer if required */ - ptimer_set_count(s->timer_cmp, tmp - s->cmp); - if ((s->cr & CR_EN)) { - /* Restart the cmp timer if required */ - ptimer_run(s->timer_cmp, 0); - } + /* It'll fire in this round of the timer */ + next = tmp - s->cmp; + } else { /* catch it next time around */ + next = tmp - s->cmp + ((s->cr & CR_RLD) ? TIMER_MAX : s->lr); } + ptimer_set_count(s->timer_cmp, next); } } @@ -237,11 +237,14 @@ static void imx_epit_write(void *opaque, { IMXEPITState *s = IMX_EPIT(opaque); uint32_t reg = offset >> 2; + uint64_t oldcr; DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg), (uint32_t)value); switch (reg) { case 0: /* CR */ + + oldcr = s->cr; s->cr = value & 0x03ffffff; if (s->cr & CR_SWR) { /* handle the reset */ @@ -250,22 +253,35 @@ static void imx_epit_write(void *opaque, imx_epit_set_freq(s); } - if (s->freq && (s->cr & CR_EN)) { + if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { if (s->cr & CR_ENMOD) { if (s->cr & CR_RLD) { ptimer_set_limit(s->timer_reload, s->lr, 1); + ptimer_set_limit(s->timer_cmp, s->lr, 1); } else { ptimer_set_limit(s->timer_reload, TIMER_MAX, 1); + ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1); } } imx_epit_reload_compare_timer(s); - - ptimer_run(s->timer_reload, 1); - } else { + ptimer_run(s->timer_reload, 0); + if (s->cr & CR_OCIEN) { + ptimer_run(s->timer_cmp, 0); + } else { + ptimer_stop(s->timer_cmp); + } + } else if (!(s->cr & CR_EN)) { /* stop both timers */ ptimer_stop(s->timer_reload); ptimer_stop(s->timer_cmp); + } else if (s->cr & CR_OCIEN) { + if (!(oldcr & CR_OCIEN)) { + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_cmp, 0); + } + } else { + ptimer_stop(s->timer_cmp); } break; @@ -284,13 +300,13 @@ static void imx_epit_write(void *opaque, /* Also set the limit if the LRD bit is set */ /* If IOVW bit is set then set the timer value */ ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); + ptimer_set_limit(s->timer_cmp, s->lr, 0); } else if (s->cr & CR_IOVW) { /* If IOVW bit is set then set the timer value */ ptimer_set_count(s->timer_reload, s->lr); } imx_epit_reload_compare_timer(s); - break; case 3: /* CMP */ @@ -306,51 +322,14 @@ static void imx_epit_write(void *opaque, break; } } - -static void imx_epit_timeout(void *opaque) -{ - IMXEPITState *s = IMX_EPIT(opaque); - - DPRINTF("\n"); - - if (!(s->cr & CR_EN)) { - return; - } - - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, TIMER_MAX, 1); - } - - if (s->cr & CR_OCIEN) { - /* if compare register is 0 then we handle the interrupt here */ - if (s->cmp == 0) { - s->sr = 1; - imx_epit_update_int(s); - } else if (s->cmp <= s->lr) { - /* We should launch the compare register */ - ptimer_set_count(s->timer_cmp, s->lr - s->cmp); - ptimer_run(s->timer_cmp, 0); - } else { - IPRINTF("s->lr < s->cmp\n"); - } - } -} - static void imx_epit_cmp(void *opaque) { IMXEPITState *s = IMX_EPIT(opaque); - DPRINTF("\n"); - - ptimer_stop(s->timer_cmp); + DPRINTF("sr was %d\n", s->sr); - /* compare register is not 0 */ - if (s->cmp) { - s->sr = 1; - imx_epit_update_int(s); - } + s->sr = 1; + imx_epit_update_int(s); } void imx_timerp_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm) @@ -400,8 +379,7 @@ static void imx_epit_realize(DeviceState 0x00001000); sysbus_init_mmio(sbd, &s->iomem); - bh = qemu_bh_new(imx_epit_timeout, s); - s->timer_reload = ptimer_init(bh); + s->timer_reload = ptimer_init(NULL); bh = qemu_bh_new(imx_epit_cmp, s); s->timer_cmp = ptimer_init(bh);