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Date: Wed, 19 Jul 2023 19:32:57 -0700 Message-Id: <81df51e9bd547f1826d67834a0d705977d7e1435.1689819032.git.tjeznach@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=tjeznach@rivosinc.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use iommu index as process identifier, linking transaction memory attributes with translation request. Signed-off-by: Tomasz Jeznach --- hw/riscv/riscv-iommu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index fd271b2988..62525df2e2 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2236,6 +2236,12 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp) /* Report QEMU target physical address space limits */ s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, TARGET_PHYS_ADDR_SPACE_BITS); + /* Restricted to the size of MemTxAttrs.pasid field. */ + if (s->cap & RISCV_IOMMU_CAP_PD8) { + MemTxAttrs attrs = { .pasid = ~0 }; + s->pasid_bits = ctz32(~((unsigned)attrs.pasid)); + } + /* Adjust reported PD capabilities */ if (s->pasid_bits < 20) { s->cap &= ~RISCV_IOMMU_CAP_PD20; @@ -2506,12 +2512,13 @@ void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, static int riscv_iommu_memory_region_index(IOMMUMemoryRegion *iommu_mr, MemTxAttrs attrs) { - return RISCV_IOMMU_NOPASID; + return attrs.unspecified ? RISCV_IOMMU_NOPASID : (int)attrs.pasid; } static int riscv_iommu_memory_region_index_len(IOMMUMemoryRegion *iommu_mr) { - return 1; + RISCVIOMMUSpace *as = container_of(iommu_mr, RISCVIOMMUSpace, iova_mr); + return 1 << as->iommu->pasid_bits; } static void riscv_iommu_memory_region_init(ObjectClass *klass, void *data)