@@ -285,12 +285,12 @@ static const MemoryRegionOps pci_ioport_ops = {
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
-static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_apb_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}
-static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_pbm_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int bus_offset;
if (pci_dev->devfn & 1)
@@ -651,7 +651,7 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
}
/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
-static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
+static int pci_bonito_map_irq(void *opaque, PCIDevice * pci_dev, int irq_num)
{
int slot;
@@ -46,7 +46,7 @@ typedef struct DECState {
PCIHostState parent_obj;
} DECState;
-static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
+static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return irq_num;
}
@@ -48,7 +48,7 @@ typedef struct GrackleState {
} GrackleState;
/* Don't know if this matches real hardware, but it agrees with OHW. */
-static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_grackle_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
@@ -874,7 +874,7 @@ static const MemoryRegionOps isd_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int gt64120_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot;
@@ -128,7 +128,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
PCIBus *bus;
for (;;) {
bus = pci_dev->bus;
- irq_num = bus->map_irq(pci_dev, irq_num);
+ irq_num = bus->map_irq(bus->irq_opaque, pci_dev, irq_num);
if (bus->set_irq)
break;
pci_dev = bus->parent_dev;
@@ -1091,7 +1091,7 @@ PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
do {
bus = dev->bus;
- pin = bus->map_irq(dev, pin);
+ pin = bus->map_irq(bus->irq_opaque, dev, pin);
dev = bus->parent_dev;
} while (dev);
assert(bus->route_intx_to_irq);
@@ -292,7 +292,7 @@ MemoryRegion *pci_address_space(PCIDevice *dev);
MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
-typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
+typedef int (*pci_map_irq_fn)(void *opaque, PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
typedef enum {
@@ -43,7 +43,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;
/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
* revision 1.2 */
/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
-static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
+static int pci_bridge_dev_map_irq_fn(void *opaque, PCIDevice *dev, int irq_num)
{
return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
}
@@ -98,7 +98,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
/* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise
mapping. */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = (pci_dev->devfn >> 3) - 1;
@@ -268,7 +268,7 @@ static void ppc4xx_pci_reset(void *opaque)
/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
* may need further refactoring for other boards. */
-static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int ppc4xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot = pci_dev->devfn >> 3;
@@ -233,7 +233,7 @@ static const MemoryRegionOps e500_pci_reg_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int mpc85xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int devno = pci_dev->devfn >> 3, ret = 0;
@@ -91,7 +91,7 @@ static const MemoryRegionOps PPC_intack_ops = {
},
};
-static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
+static int prep_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 1;
}
@@ -98,7 +98,7 @@ static const MemoryRegionOps sh_pci_reg_ops = {
},
};
-static int sh_pci_map_irq(PCIDevice *d, int irq_num)
+static int sh_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
return (d->devfn >> 3);
}
@@ -59,7 +59,7 @@ typedef struct UNINState {
MemoryRegion pci_hole;
} UNINState;
-static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_unin_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int retval;
int devfn = pci_dev->devfn & 0x00FFFFFF;
@@ -46,7 +46,7 @@ static const MemoryRegionOps pci_vpb_config_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+static int pci_vpb_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
return irq_num;
}
@@ -31,7 +31,7 @@ static inline int xen_enabled(void)
#endif
}
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
@@ -99,7 +99,7 @@ typedef struct XenIOState {
/* Xen specific function for piix pci */
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return irq_num + ((pci_dev->devfn >> 3) << 2);
}
@@ -16,7 +16,7 @@ void xenstore_store_pv_console_info(int i, CharDriverState *chr)
{
}
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return -1;
}