From patchwork Tue Jan 28 06:25:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 314595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C50CB2C0078 for ; Tue, 28 Jan 2014 17:27:10 +1100 (EST) Received: from localhost ([::1]:35483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W828a-0001PC-BW for incoming@patchwork.ozlabs.org; Tue, 28 Jan 2014 01:27:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W827I-0000TX-J8 for qemu-devel@nongnu.org; Tue, 28 Jan 2014 01:25:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W827C-0004yj-6R for qemu-devel@nongnu.org; Tue, 28 Jan 2014 01:25:48 -0500 Received: from mail-ea0-x235.google.com ([2a00:1450:4013:c01::235]:50582) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W827B-0004yR-Li for qemu-devel@nongnu.org; Tue, 28 Jan 2014 01:25:42 -0500 Received: by mail-ea0-f181.google.com with SMTP id m10so2742017eaj.12 for ; Mon, 27 Jan 2014 22:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=r2pUF/TzvVuXwUXEGSAUAbdU59RVjUPhz3NZAoYiCxk=; b=zQBbwzd3uQjp2F/hnE8u3sEnaK0bi7CDmx4ah0Z8zHwmXPqVhFy6e//R1+uzPtsZeC Q0gF8WkP+SeSHix+mHn7RLFKcr0H103lbOK8o/P7kXwoBu2yiK6laVaQjBiLOUJxSemd 4jHHZePDHQGjI+3NYanIfyPg98iJ4MieVVfyOZeGV6uzOcIwaNMHmB39wqznix8T1Ke9 iEdK549nZPCmUADUQ3j7xBxUvSSC/eW/Uwr303QbA2x4kKoiJVBcRwGGXPI+BTLJo7S5 LKkFNfrpVbBxgbI/sRiqf7lmboYxFOf+y6WfYb9+AvAADFGxkfIh5ZALovy4qcjkzC5I t7Nw== X-Received: by 10.15.73.134 with SMTP id h6mr3326113eey.15.1390890340884; Mon, 27 Jan 2014 22:25:40 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id v1sm51544486eef.9.2014.01.27.22.25.39 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 27 Jan 2014 22:25:40 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Tue, 28 Jan 2014 16:25:33 +1000 Message-Id: <7657ae91ccb054094a8105a55303ea70eff45d3c.1390890100.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c01::235 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v4 1/1] target-arm: Implements the ARM PMCCNTR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis --- This patch assumes that non-invasive debugging is not permitted when determining if the counter is disabled V4: Some bug fixes pointed out by Peter Crosthwaite. Including increasing the accuracy of the timer. V3: Fixed up incorrect reset, disable and enable handling that was submitted in V2. The patch should now also handle changing of the clock scaling. V2: Incorporated the comments that Peter Maydell and Peter Crosthwaite had. Now the implementation only requires one CPU state target-arm/cpu.h | 3 ++ target-arm/helper.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 198b6b8..2fdab58 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -215,6 +215,9 @@ typedef struct CPUARMState { uint32_t c15_diagnostic; /* diagnostic register */ uint32_t c15_power_diagnostic; uint32_t c15_power_control; /* power control */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value */ + uint32_t c15_ccnt; } cp15; /* System registers (AArch64) */ diff --git a/target-arm/helper.c b/target-arm/helper.c index c708f15..f6c57c8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,6 +13,12 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, target_ulong *page_size); #endif +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRDP 0x20 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -502,12 +508,46 @@ static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri, static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + uint32_t temp_ticks; + if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { return EXCP_UDEF; } + + temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + /* This assumes that non-invasive debugging is not permitted */ + if (!(env->cp15.c9_pmcr & PMCRDP) || + env->cp15.c9_pmcr & PMCRE) { + /* If the counter is enabled */ + if (env->cp15.c9_pmcr & PMCRDP) { + /* Increment once every 64 processor clock cycles */ + env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; + } else { + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } + } + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + /* This assumes that non-invasive debugging is not permitted */ + if (!(env->cp15.c9_pmcr & PMCRDP) || + env->cp15.c9_pmcr & PMCRE) { + if (env->cp15.c9_pmcr & PMCRDP) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /= 64; + } + env->cp15.c15_ccnt = temp_ticks; + } + return 0; } @@ -584,6 +624,39 @@ static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + uint32_t total_ticks; + + /* This assumes that non-invasive debugging is not permitted */ + if (env->cp15.c9_pmcr & PMCRDP || + !(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + *value = env->cp15.c15_ccnt; + return 0; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRDP) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + *value = total_ticks - env->cp15.c15_ccnt; + + return 0; +} + +static int pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* A NOP write */ + qemu_log_mask(LOG_UNIMP, "CCNT: Write not implemented\n"); + return 0; +} + static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -644,9 +717,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - /* Unimplemented, RAZ/WI. XXX PMUSERENR */ { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_RW, .readfn = pmccntr_read, .writefn = pmccntr_write, + .resetvalue = 0, .type = ARM_CP_IO }, { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),