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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , Aurelien Jarno , Marcel Apfelbaum , =?utf-8?b?SGVydsOp?= Poussineau Subject: [PULL v3 39/62] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Message-ID: <74bdcfb4b2ba7958efe8e66e06757579d61ebbb3.1697966402.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Bernhard Beschow PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the same structure, provided in a public header. So reuse it and add a cpu_intr attribute to it which is only used by PIIX4. Signed-off-by: Bernhard Beschow Message-Id: <20231007123843.127151-19-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/southbridge/piix.h | 1 + hw/isa/piix4.c | 26 +++++++++++--------------- 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 0b257e1582..dd5f7b31c0 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -49,6 +49,7 @@ struct PIIXState { #endif uint64_t pic_levels; + qemu_irq cpu_intr; qemu_irq isa_irqs_in[ISA_NUM_IRQS]; /* This member isn't used. Just for save/load compatibility */ diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index eb456622c5..71899aaa69 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -42,21 +42,9 @@ #include "sysemu/runstate.h" #include "qom/object.h" -struct PIIX4State { - PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa_irqs_in; +typedef struct PIIXState PIIX4State; - MC146818RtcState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) +DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVICE) static void piix4_set_irq(void *opaque, int irq_num, int level) { @@ -184,6 +172,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; + qemu_irq *i8259; + size_t i; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -201,7 +191,13 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* initialize i8259 pic */ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa_irqs_in = i8259_init(isa_bus, *i8259_out_irq); + i8259 = i8259_init(isa_bus, *i8259_out_irq); + + for (i = 0; i < ISA_NUM_IRQS; i++) { + s->isa_irqs_in[i] = i8259[i]; + } + + g_free(i8259); /* initialize ISA irqs */ isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);