From patchwork Mon Mar 19 22:57:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 147686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CF325B6FA7 for ; Tue, 20 Mar 2012 10:49:37 +1100 (EST) Received: from localhost ([::1]:37068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lYh-0005Wv-4j for incoming@patchwork.ozlabs.org; Mon, 19 Mar 2012 19:00:11 -0400 Received: from eggs.gnu.org ([208.118.235.92]:55848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lXI-000395-Dk for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S9lX9-00011J-2E for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:14956) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lX8-00010u-Nl for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:34 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q2JMwXgM022765 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 19 Mar 2012 18:58:33 -0400 Received: from trasno.mitica (ovpn-116-17.ams2.redhat.com [10.36.116.17]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q2JMw4oc017718; Mon, 19 Mar 2012 18:58:32 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2012 23:57:50 +0100 Message-Id: <6c88b8c31d40934315f2c703c618847bc4580823.1332197811.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 22/36] vmstate: port mips cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Juan Quintela --- target-mips/cpu.h | 5 +- target-mips/machine.c | 465 +++++++++++++++++++------------------------------ 2 files changed, 182 insertions(+), 288 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index d2773d6..2475d32 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -37,6 +37,9 @@ struct r4k_tlb_t { uint_fast16_t D0:1; uint_fast16_t D1:1; target_ulong PFN[2]; + /* Fields needed as intermediate for vmstate */ + uint8_t asid_vmstate; + uint16_t flags_vmstate; }; #if !defined(CONFIG_USER_ONLY) @@ -507,8 +510,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list -#define CPU_SAVE_VERSION 4 - /* MMU modes definitions. We carefully match the indices with our hflags layout. */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-mips/machine.c b/target-mips/machine.c index 8b9c0fb..8951748 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -3,304 +3,197 @@ #include "cpu.h" -static void save_tc(QEMUFile *f, TCState *tc) -{ - int i; - - /* Save active TC */ - for(i = 0; i < 32; i++) - qemu_put_betls(f, &tc->gpr[i]); - qemu_put_betls(f, &tc->PC); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_put_betls(f, &tc->HI[i]); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_put_betls(f, &tc->LO[i]); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_put_betls(f, &tc->ACX[i]); - qemu_put_betls(f, &tc->DSPControl); - qemu_put_sbe32s(f, &tc->CP0_TCStatus); - qemu_put_sbe32s(f, &tc->CP0_TCBind); - qemu_put_betls(f, &tc->CP0_TCHalt); - qemu_put_betls(f, &tc->CP0_TCContext); - qemu_put_betls(f, &tc->CP0_TCSchedule); - qemu_put_betls(f, &tc->CP0_TCScheFBack); - qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); -} - -static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) -{ - int i; - - for(i = 0; i < 32; i++) - qemu_put_be64s(f, &fpu->fpr[i].d); - qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); - qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); - qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); - qemu_put_be32s(f, &fpu->fcr0); - qemu_put_be32s(f, &fpu->fcr31); -} - -void cpu_save(QEMUFile *f, void *opaque) -{ - CPUMIPSState *env = opaque; - int i; - - /* Save active TC */ - save_tc(f, &env->active_tc); - - /* Save active FPU */ - save_fpu(f, &env->active_fpu); - - /* Save MVP */ - qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl); - qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0); - qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1); - - /* Save TLB */ - qemu_put_be32s(f, &env->tlb.nb_tlb); - qemu_put_be32s(f, &env->tlb.tlb_in_use); - for(i = 0; i < MIPS_TLB_MAX; i++) { - uint16_t flags = ((env->tlb.mmu.r4k.tlb[i].G << 10) | - (env->tlb.mmu.r4k.tlb[i].C0 << 7) | - (env->tlb.mmu.r4k.tlb[i].C1 << 4) | - (env->tlb.mmu.r4k.tlb[i].V0 << 3) | - (env->tlb.mmu.r4k.tlb[i].V1 << 2) | - (env->tlb.mmu.r4k.tlb[i].D0 << 1) | - (env->tlb.mmu.r4k.tlb[i].D1 << 0)); - uint8_t asid; - - qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN); - qemu_put_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask); - asid = env->tlb.mmu.r4k.tlb[i].ASID; - qemu_put_8s(f, &asid); - qemu_put_be16s(f, &flags); - qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]); - qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]); +static const VMStateDescription vmstate_tc = { + .name = "tc", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), + VMSTATE_UINTTL(PC, TCState), + VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), + VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), + VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), + VMSTATE_UINTTL(DSPControl, TCState), + VMSTATE_INT32(CP0_TCStatus, TCState), + VMSTATE_INT32(CP0_TCBind, TCState), + VMSTATE_UINTTL(CP0_TCHalt, TCState), + VMSTATE_UINTTL(CP0_TCContext, TCState), + VMSTATE_UINTTL(CP0_TCSchedule, TCState), + VMSTATE_UINTTL(CP0_TCScheFBack, TCState), + VMSTATE_INT32(CP0_Debug_tcstatus, TCState), + VMSTATE_END_OF_LIST() } +}; + +static const VMStateDescription vmstate_fpu_reg = { + .name = "fpu_reg", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64(d, fpr_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_fpu_context = { + .name = "fpu_context", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(fpr, CPUMIPSFPUContext, 32, 0, + vmstate_fpu_reg, fpr_t), + VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext), + VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext), + VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext), + VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), + VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), + VMSTATE_END_OF_LIST() + } +}; - /* Save CPU metastate */ - qemu_put_be32s(f, &env->current_tc); - qemu_put_be32s(f, &env->current_fpu); - qemu_put_sbe32s(f, &env->error_code); - qemu_put_be32s(f, &env->hflags); - qemu_put_betls(f, &env->btarget); - qemu_put_betls(f, &env->bcond); - - /* Save remaining CP1 registers */ - qemu_put_sbe32s(f, &env->CP0_Index); - qemu_put_sbe32s(f, &env->CP0_Random); - qemu_put_sbe32s(f, &env->CP0_VPEControl); - qemu_put_sbe32s(f, &env->CP0_VPEConf0); - qemu_put_sbe32s(f, &env->CP0_VPEConf1); - qemu_put_betls(f, &env->CP0_YQMask); - qemu_put_betls(f, &env->CP0_VPESchedule); - qemu_put_betls(f, &env->CP0_VPEScheFBack); - qemu_put_sbe32s(f, &env->CP0_VPEOpt); - qemu_put_betls(f, &env->CP0_EntryLo0); - qemu_put_betls(f, &env->CP0_EntryLo1); - qemu_put_betls(f, &env->CP0_Context); - qemu_put_sbe32s(f, &env->CP0_PageMask); - qemu_put_sbe32s(f, &env->CP0_PageGrain); - qemu_put_sbe32s(f, &env->CP0_Wired); - qemu_put_sbe32s(f, &env->CP0_SRSConf0); - qemu_put_sbe32s(f, &env->CP0_SRSConf1); - qemu_put_sbe32s(f, &env->CP0_SRSConf2); - qemu_put_sbe32s(f, &env->CP0_SRSConf3); - qemu_put_sbe32s(f, &env->CP0_SRSConf4); - qemu_put_sbe32s(f, &env->CP0_HWREna); - qemu_put_betls(f, &env->CP0_BadVAddr); - qemu_put_sbe32s(f, &env->CP0_Count); - qemu_put_betls(f, &env->CP0_EntryHi); - qemu_put_sbe32s(f, &env->CP0_Compare); - qemu_put_sbe32s(f, &env->CP0_Status); - qemu_put_sbe32s(f, &env->CP0_IntCtl); - qemu_put_sbe32s(f, &env->CP0_SRSCtl); - qemu_put_sbe32s(f, &env->CP0_SRSMap); - qemu_put_sbe32s(f, &env->CP0_Cause); - qemu_put_betls(f, &env->CP0_EPC); - qemu_put_sbe32s(f, &env->CP0_PRid); - qemu_put_sbe32s(f, &env->CP0_EBase); - qemu_put_sbe32s(f, &env->CP0_Config0); - qemu_put_sbe32s(f, &env->CP0_Config1); - qemu_put_sbe32s(f, &env->CP0_Config2); - qemu_put_sbe32s(f, &env->CP0_Config3); - qemu_put_sbe32s(f, &env->CP0_Config6); - qemu_put_sbe32s(f, &env->CP0_Config7); - qemu_put_betls(f, &env->lladdr); - for(i = 0; i < 8; i++) - qemu_put_betls(f, &env->CP0_WatchLo[i]); - for(i = 0; i < 8; i++) - qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); - qemu_put_betls(f, &env->CP0_XContext); - qemu_put_sbe32s(f, &env->CP0_Framemask); - qemu_put_sbe32s(f, &env->CP0_Debug); - qemu_put_betls(f, &env->CP0_DEPC); - qemu_put_sbe32s(f, &env->CP0_Performance0); - qemu_put_sbe32s(f, &env->CP0_TagLo); - qemu_put_sbe32s(f, &env->CP0_DataLo); - qemu_put_sbe32s(f, &env->CP0_TagHi); - qemu_put_sbe32s(f, &env->CP0_DataHi); - qemu_put_betls(f, &env->CP0_ErrorEPC); - qemu_put_sbe32s(f, &env->CP0_DESAVE); - - /* Save inactive TC state */ - for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) - save_tc(f, &env->tcs[i]); - for (i = 0; i < MIPS_FPU_MAX; i++) - save_fpu(f, &env->fpus[i]); -} - -static void load_tc(QEMUFile *f, TCState *tc) +static void tlb_pre_save(void *opaque) { - int i; - - /* Save active TC */ - for(i = 0; i < 32; i++) - qemu_get_betls(f, &tc->gpr[i]); - qemu_get_betls(f, &tc->PC); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_get_betls(f, &tc->HI[i]); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_get_betls(f, &tc->LO[i]); - for(i = 0; i < MIPS_DSP_ACC; i++) - qemu_get_betls(f, &tc->ACX[i]); - qemu_get_betls(f, &tc->DSPControl); - qemu_get_sbe32s(f, &tc->CP0_TCStatus); - qemu_get_sbe32s(f, &tc->CP0_TCBind); - qemu_get_betls(f, &tc->CP0_TCHalt); - qemu_get_betls(f, &tc->CP0_TCContext); - qemu_get_betls(f, &tc->CP0_TCSchedule); - qemu_get_betls(f, &tc->CP0_TCScheFBack); - qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); + r4k_tlb_t *tlb = opaque; + + tlb->asid_vmstate = tlb->ASID; + tlb->flags_vmstate = ((tlb->G << 10) | + (tlb->C0 << 7) | + (tlb->C1 << 4) | + (tlb->V0 << 3) | + (tlb->V1 << 2) | + (tlb->D0 << 1) | + (tlb->D1 << 0)); } -static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) +static int tlb_post_load(void *opaque, int version_id) { - int i; - - for(i = 0; i < 32; i++) - qemu_get_be64s(f, &fpu->fpr[i].d); - qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); - qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); - qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); - qemu_get_be32s(f, &fpu->fcr0); - qemu_get_be32s(f, &fpu->fcr31); + r4k_tlb_t *tlb = opaque; + + tlb->ASID = tlb->asid_vmstate; + tlb->G = (tlb->flags_vmstate >> 10) & 1; + tlb->C0 = (tlb->flags_vmstate >> 7) & 3; + tlb->C1 = (tlb->flags_vmstate >> 4) & 3; + tlb->V0 = (tlb->flags_vmstate >> 3) & 1; + tlb->V1 = (tlb->flags_vmstate >> 2) & 1; + tlb->D0 = (tlb->flags_vmstate >> 1) & 1; + tlb->D1 = (tlb->flags_vmstate >> 0) & 1; + return 0; } -int cpu_load(QEMUFile *f, void *opaque, int version_id) -{ - CPUMIPSState *env = opaque; - int i; - - if (version_id != 4) { - return -EINVAL; - } - /* Load active TC */ - load_tc(f, &env->active_tc); - - /* Load active FPU */ - load_fpu(f, &env->active_fpu); - - /* Load MVP */ - qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl); - qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0); - qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1); - - /* Load TLB */ - qemu_get_be32s(f, &env->tlb.nb_tlb); - qemu_get_be32s(f, &env->tlb.tlb_in_use); - for(i = 0; i < MIPS_TLB_MAX; i++) { - uint16_t flags; - uint8_t asid; - - qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN); - qemu_get_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask); - qemu_get_8s(f, &asid); - env->tlb.mmu.r4k.tlb[i].ASID = asid; - qemu_get_be16s(f, &flags); - env->tlb.mmu.r4k.tlb[i].G = (flags >> 10) & 1; - env->tlb.mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; - env->tlb.mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; - env->tlb.mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; - env->tlb.mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; - env->tlb.mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; - env->tlb.mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; - qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]); - qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]); +static const VMStateDescription vmstate_tlb = { + .name = "tlb", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .pre_save = tlb_pre_save, + .post_load = tlb_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(VPN, r4k_tlb_t), + VMSTATE_UINT32(PageMask, r4k_tlb_t), + VMSTATE_UINT8(asid_vmstate, r4k_tlb_t), + VMSTATE_UINT16(flags_vmstate, r4k_tlb_t), + VMSTATE_UINTTL_ARRAY(PFN, r4k_tlb_t, 2), + VMSTATE_END_OF_LIST() } +}; - /* Load CPU metastate */ - qemu_get_be32s(f, &env->current_tc); - qemu_get_be32s(f, &env->current_fpu); - qemu_get_sbe32s(f, &env->error_code); - qemu_get_be32s(f, &env->hflags); - qemu_get_betls(f, &env->btarget); - qemu_get_betls(f, &env->bcond); - - /* Load remaining CP1 registers */ - qemu_get_sbe32s(f, &env->CP0_Index); - qemu_get_sbe32s(f, &env->CP0_Random); - qemu_get_sbe32s(f, &env->CP0_VPEControl); - qemu_get_sbe32s(f, &env->CP0_VPEConf0); - qemu_get_sbe32s(f, &env->CP0_VPEConf1); - qemu_get_betls(f, &env->CP0_YQMask); - qemu_get_betls(f, &env->CP0_VPESchedule); - qemu_get_betls(f, &env->CP0_VPEScheFBack); - qemu_get_sbe32s(f, &env->CP0_VPEOpt); - qemu_get_betls(f, &env->CP0_EntryLo0); - qemu_get_betls(f, &env->CP0_EntryLo1); - qemu_get_betls(f, &env->CP0_Context); - qemu_get_sbe32s(f, &env->CP0_PageMask); - qemu_get_sbe32s(f, &env->CP0_PageGrain); - qemu_get_sbe32s(f, &env->CP0_Wired); - qemu_get_sbe32s(f, &env->CP0_SRSConf0); - qemu_get_sbe32s(f, &env->CP0_SRSConf1); - qemu_get_sbe32s(f, &env->CP0_SRSConf2); - qemu_get_sbe32s(f, &env->CP0_SRSConf3); - qemu_get_sbe32s(f, &env->CP0_SRSConf4); - qemu_get_sbe32s(f, &env->CP0_HWREna); - qemu_get_betls(f, &env->CP0_BadVAddr); - qemu_get_sbe32s(f, &env->CP0_Count); - qemu_get_betls(f, &env->CP0_EntryHi); - qemu_get_sbe32s(f, &env->CP0_Compare); - qemu_get_sbe32s(f, &env->CP0_Status); - qemu_get_sbe32s(f, &env->CP0_IntCtl); - qemu_get_sbe32s(f, &env->CP0_SRSCtl); - qemu_get_sbe32s(f, &env->CP0_SRSMap); - qemu_get_sbe32s(f, &env->CP0_Cause); - qemu_get_betls(f, &env->CP0_EPC); - qemu_get_sbe32s(f, &env->CP0_PRid); - qemu_get_sbe32s(f, &env->CP0_EBase); - qemu_get_sbe32s(f, &env->CP0_Config0); - qemu_get_sbe32s(f, &env->CP0_Config1); - qemu_get_sbe32s(f, &env->CP0_Config2); - qemu_get_sbe32s(f, &env->CP0_Config3); - qemu_get_sbe32s(f, &env->CP0_Config6); - qemu_get_sbe32s(f, &env->CP0_Config7); - qemu_get_betls(f, &env->lladdr); - for(i = 0; i < 8; i++) - qemu_get_betls(f, &env->CP0_WatchLo[i]); - for(i = 0; i < 8; i++) - qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); - qemu_get_betls(f, &env->CP0_XContext); - qemu_get_sbe32s(f, &env->CP0_Framemask); - qemu_get_sbe32s(f, &env->CP0_Debug); - qemu_get_betls(f, &env->CP0_DEPC); - qemu_get_sbe32s(f, &env->CP0_Performance0); - qemu_get_sbe32s(f, &env->CP0_TagLo); - qemu_get_sbe32s(f, &env->CP0_DataLo); - qemu_get_sbe32s(f, &env->CP0_TagHi); - qemu_get_sbe32s(f, &env->CP0_DataHi); - qemu_get_betls(f, &env->CP0_ErrorEPC); - qemu_get_sbe32s(f, &env->CP0_DESAVE); - - /* Load inactive TC state */ - for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) - load_tc(f, &env->tcs[i]); - for (i = 0; i < MIPS_FPU_MAX; i++) - load_fpu(f, &env->fpus[i]); +static int cpu_post_load(void *opaque, int version_id) +{ + CPUMIPSState *env = opaque; /* XXX: ensure compatibility for halted bit ? */ tlb_flush(env, 1); return 0; } + +const VMStateDescription vmstate_cpu = { + .name = "cpu", + .version_id = 4, + .minimum_version_id = 4, + .minimum_version_id_old = 4, + .post_load = cpu_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT(active_tc, CPUMIPSState, 0, vmstate_tc, TCState), + VMSTATE_STRUCT(active_fpu, CPUMIPSState, 0, vmstate_fpu_context, + CPUMIPSFPUContext), + /* Save MVP */ + VMSTATE_INT32(mvp.CP0_MVPControl, CPUMIPSState), + VMSTATE_INT32(mvp.CP0_MVPConf0, CPUMIPSState), + VMSTATE_INT32(mvp.CP0_MVPConf1, CPUMIPSState), + /* Save TLB */ + VMSTATE_UINT32(tlb.nb_tlb, CPUMIPSState), + VMSTATE_UINT32(tlb.tlb_in_use, CPUMIPSState), + VMSTATE_STRUCT_ARRAY(tlb.mmu.r4k.tlb, CPUMIPSState, MIPS_TLB_MAX, 0, + vmstate_tlb, r4k_tlb_t), + /* Save CPU metastate */ + VMSTATE_UINT32(current_tc, CPUMIPSState), + VMSTATE_UINT32(current_fpu, CPUMIPSState), + VMSTATE_INT32(error_code, CPUMIPSState), + VMSTATE_UINT32(hflags, CPUMIPSState), + VMSTATE_UINTTL(btarget, CPUMIPSState), + VMSTATE_UINTTL(bcond, CPUMIPSState), + /* Save remaining CP1 registers */ + VMSTATE_INT32(CP0_Index, CPUMIPSState), + VMSTATE_INT32(CP0_Random, CPUMIPSState), + VMSTATE_INT32(CP0_VPEControl, CPUMIPSState), + VMSTATE_INT32(CP0_VPEConf0, CPUMIPSState), + VMSTATE_INT32(CP0_VPEConf1, CPUMIPSState), + VMSTATE_UINTTL(CP0_YQMask, CPUMIPSState), + VMSTATE_UINTTL(CP0_VPESchedule, CPUMIPSState), + VMSTATE_UINTTL(CP0_VPEScheFBack, CPUMIPSState), + VMSTATE_INT32(CP0_VPEOpt, CPUMIPSState), + VMSTATE_UINTTL(CP0_EntryLo0, CPUMIPSState), + VMSTATE_UINTTL(CP0_EntryLo1, CPUMIPSState), + VMSTATE_UINTTL(CP0_Context, CPUMIPSState), + VMSTATE_INT32(CP0_PageMask, CPUMIPSState), + VMSTATE_INT32(CP0_PageGrain, CPUMIPSState), + VMSTATE_INT32(CP0_Wired, CPUMIPSState), + VMSTATE_INT32(CP0_SRSConf0, CPUMIPSState), + VMSTATE_INT32(CP0_SRSConf1, CPUMIPSState), + VMSTATE_INT32(CP0_SRSConf2, CPUMIPSState), + VMSTATE_INT32(CP0_SRSConf3, CPUMIPSState), + VMSTATE_INT32(CP0_SRSConf4, CPUMIPSState), + VMSTATE_INT32(CP0_HWREna, CPUMIPSState), + VMSTATE_UINTTL(CP0_BadVAddr, CPUMIPSState), + VMSTATE_INT32(CP0_Count, CPUMIPSState), + VMSTATE_UINTTL(CP0_EntryHi, CPUMIPSState), + VMSTATE_INT32(CP0_Compare, CPUMIPSState), + VMSTATE_INT32(CP0_Status, CPUMIPSState), + VMSTATE_INT32(CP0_IntCtl, CPUMIPSState), + VMSTATE_INT32(CP0_SRSCtl, CPUMIPSState), + VMSTATE_INT32(CP0_SRSMap, CPUMIPSState), + VMSTATE_INT32(CP0_Cause, CPUMIPSState), + VMSTATE_UINTTL(CP0_EPC, CPUMIPSState), + VMSTATE_INT32(CP0_PRid, CPUMIPSState), + VMSTATE_INT32(CP0_EBase, CPUMIPSState), + VMSTATE_INT32(CP0_Config0, CPUMIPSState), + VMSTATE_INT32(CP0_Config1, CPUMIPSState), + VMSTATE_INT32(CP0_Config2, CPUMIPSState), + VMSTATE_INT32(CP0_Config3, CPUMIPSState), + VMSTATE_INT32(CP0_Config6, CPUMIPSState), + VMSTATE_INT32(CP0_Config7, CPUMIPSState), + VMSTATE_UINTTL(lladdr, CPUMIPSState), + VMSTATE_UINTTL_ARRAY(CP0_WatchLo, CPUMIPSState, 8), + VMSTATE_INT32_ARRAY(CP0_WatchHi, CPUMIPSState, 8), + VMSTATE_UINTTL(CP0_XContext, CPUMIPSState), + VMSTATE_INT32(CP0_Framemask, CPUMIPSState), + VMSTATE_INT32(CP0_Debug, CPUMIPSState), + VMSTATE_UINTTL(CP0_DEPC, CPUMIPSState), + VMSTATE_INT32(CP0_Performance0, CPUMIPSState), + VMSTATE_INT32(CP0_TagLo, CPUMIPSState), + VMSTATE_INT32(CP0_DataLo, CPUMIPSState), + VMSTATE_INT32(CP0_TagHi, CPUMIPSState), + VMSTATE_INT32(CP0_DataHi, CPUMIPSState), + VMSTATE_UINTTL(CP0_ErrorEPC, CPUMIPSState), + VMSTATE_INT32(CP0_DESAVE, CPUMIPSState), + /* Save inactive TC state */ + VMSTATE_STRUCT_ARRAY(tcs, CPUMIPSState, MIPS_SHADOW_SET_MAX, 0, + vmstate_tc, TCState), + VMSTATE_STRUCT_ARRAY(fpus, CPUMIPSState, MIPS_FPU_MAX, 0, + vmstate_fpu_context, CPUMIPSFPUContext), + VMSTATE_END_OF_LIST() + }, +};