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Sat, 30 Jan 2016 01:03:33 +0000 Received: from 172-16-1-203.xilinx.com ([172.16.1.203]:45466 helo=xsj-tvapsmtp02.xilinx.com) by xsj-tvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1aPJwr-0002NW-B5; Fri, 29 Jan 2016 17:03:33 -0800 Received: from [127.0.0.1] (port=52685 helo=tsj-smtp-dlp1.xlnx.xilinx.com) by xsj-tvapsmtp02.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1aPJwr-0002tN-5F; Fri, 29 Jan 2016 17:03:33 -0800 Received: from xsj-tvapsmtp02 (xsj-tvapsmtp02.xilinx.com [172.16.1.203]) by tsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u0U0vuXo022021; Fri, 29 Jan 2016 16:57:56 -0800 Received: from [172.19.74.182] (port=49974 helo=xsjalistai50.xlnx.xilinx.com) by xsj-tvapsmtp02 with esmtp (Exim 4.63) (envelope-from ) id 1aPJwq-0002tK-D5; Fri, 29 Jan 2016 17:03:32 -0800 From: Alistair Francis To: , , Date: Fri, 29 Jan 2016 17:00:56 -0800 Message-ID: <6c273c2fd27808974c51bf3562beed6e403364c3.1454115217.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22054.006 X-TM-AS-Result: No--11.969-7.0-31-10 X-imss-scan-details: No--11.969-7.0-31-10 X-TMASE-MatchedRID: MpG/zcNZUvH/uyguzMmOKBWCVBr+Ay98Ebs7d+z9c8s4YKAM3oRt9t79 oseDjSdCkZ3T6ylBNAWvXn8ZlTtgDIRSqwm2ppCS3fn7n/ZHGqY7r2Gtb9iBYdjxT3jt1KNe7li gIqDOzwuDnZGblAfgjTMosKBshIlQbwt0+Smt6YeO0rt0LpQGebVNU7DO2GYB8ayRINFASnDejM lFftvg2cuoIlmzRW7AauCY++1iRsu+FLmfZ5YAokhwlOfYeSqxGbJMFqqIm9xQR7Hmcp1pNaPFj JEFr+olwXCBO/GKkVqOhzOa6g8KrQ7wZ7nzzevGLyhr2ocYkxQIl3O4HbCiwaeKDR4g5yJTsfvS 8H9R3wY= X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.96; 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PCL:0; RULEID:(601004)(2401047)(13015025)(13017025)(13023025)(5005006)(8121501046)(13018025)(13024025)(10201501046)(3002001); SRVR:BL2NAM02HT034; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT034; X-Forefront-PRVS: 083751FCA6 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2016 01:03:33.9667 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT034 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.38.55 Cc: edgar.iglesias@xilinx.com, edgar.iglesias@gmail.com, crosthwaitepeter@gmail.com, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v3 06/16] register: QOMify X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite QOMify registers as a child of TYPE_DEVICE. This allows registers to define GPIOs. Define an init helper that will do QOM initialisation as well as setup the r/w fast paths. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis Reviewed-by: KONRAD Frederic --- hw/core/register.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/register.h | 14 ++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/hw/core/register.c b/hw/core/register.c index e696c43..939f398 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -188,6 +188,28 @@ void register_reset(RegisterInfo *reg) register_write_val(reg, reg->access->reset); } +void register_init(RegisterInfo *reg) +{ + assert(reg); + const RegisterAccessInfo *ac; + + if (!reg->data || !reg->access) { + return; + } + + object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER); + + ac = reg->access; + + /* if there are no debug msgs and no RMW requirement, mark for fast write */ + reg->write_lite = reg->debug || ac->ro || ac->w1c || ac->pre_write || + ((ac->ge0 || ac->ge1) && qemu_loglevel_mask(LOG_GUEST_ERROR)) || + ((ac->ui0 || ac->ui1) && qemu_loglevel_mask(LOG_UNIMP)) + ? false : true; + /* no debug and no clear-on-read is a fast read */ + reg->read_lite = reg->debug || ac->cor ? false : true; +} + static inline void register_write_memory(void *opaque, hwaddr addr, uint64_t value, unsigned size, bool be) { @@ -235,3 +257,15 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size) { return register_read_memory(opaque, addr, size, false); } + +static const TypeInfo register_info = { + .name = TYPE_REGISTER, + .parent = TYPE_DEVICE, +}; + +static void register_register_types(void) +{ + type_register_static(®ister_info); +} + +type_init(register_register_types) diff --git a/include/hw/register.h b/include/hw/register.h index 38ee6f5..3316458 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -11,6 +11,7 @@ #ifndef REGISTER_H #define REGISTER_H +#include "hw/qdev-core.h" #include "exec/memory.h" typedef struct RegisterInfo RegisterInfo; @@ -101,6 +102,8 @@ struct RegisterAccessInfo { struct RegisterInfo { /* */ + DeviceState parent_obj; + bool read_lite; bool write_lite; @@ -118,6 +121,9 @@ struct RegisterInfo { void *opaque; }; +#define TYPE_REGISTER "qemu,register" +#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER) + /** * write a value to a register, subject to its restrictions * @reg: register to write to @@ -143,6 +149,14 @@ uint64_t register_read(RegisterInfo *reg); void register_reset(RegisterInfo *reg); /** + * Initialize a register. GPIO's are setup as IOs to the specified device. + * Fast paths for eligible registers are enabled. + * @reg: Register to initialize + */ + +void register_init(RegisterInfo *reg); + +/** * Memory API MMIO write handler that will write to a Register API register. * _be for big endian variant and _le for little endian. * @opaque: RegisterInfo to write to