From patchwork Tue Mar 22 22:59:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 87969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9420DB6EF7 for ; Wed, 23 Mar 2011 10:05:06 +1100 (EST) Received: from localhost ([127.0.0.1]:44074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q2AdL-0006vF-R4 for incoming@patchwork.ozlabs.org; Tue, 22 Mar 2011 19:05:03 -0400 Received: from [140.186.70.92] (port=54480 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q2AY3-0004bG-GU for qemu-devel@nongnu.org; Tue, 22 Mar 2011 18:59:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q2AY2-0007as-8Q for qemu-devel@nongnu.org; Tue, 22 Mar 2011 18:59:35 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:46277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q2AY0-0007a7-QY for qemu-devel@nongnu.org; Tue, 22 Mar 2011 18:59:34 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id A290418928; Wed, 23 Mar 2011 07:59:28 +0900 (JST) Received: (nullmailer pid 13834 invoked by uid 1000); Tue, 22 Mar 2011 22:59:28 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Wed, 23 Mar 2011 07:59:26 +0900 Message-Id: <6bb6047e9311e46ee16c43b2ae86d56186133f18.1300834490.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 210.128.90.3 Cc: yamahata@valinux.co.jp, Juan Quintela , mst@redhat.com Subject: [Qemu-devel] [PATCH v4 2/4] piix_pci: eliminate PIIX3State::pci_irq_levels X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org PIIX3State::pci_irq_levels are redundant which is already tracked by PCIBus layer. So eliminate them. Cc: Juan Quintela Cc: Michael S. Tsirkin Signed-off-by: Isaku Yamahata --- Changes v3 -> v4: - use PCI_NUM_PINS instead of magic number 4 Changes v2 -> v3: - rename member s/dummy_for_save_load_compat/pci_irq_levels_vmstate/g --- hw/piix_pci.c | 34 ++++++++++++++++++++++++---------- 1 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 358da58..ad63146 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -39,8 +39,10 @@ typedef PCIHostState I440FXState; typedef struct PIIX3State { PCIDevice dev; - int pci_irq_levels[4]; qemu_irq *pic; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PCI_NUM_PINS]; } PIIX3State; struct PCII440FXState { @@ -162,9 +164,11 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) i440fx_update_memory_mappings(d); qemu_get_8s(f, &d->smm_enabled); - if (version_id == 2) - for (i = 0; i < 4; i++) - d->piix3->pci_irq_levels[i] = qemu_get_be32(f); + if (version_id == 2) { + for (i = 0; i < 4; i++) { + qemu_get_be32(f); /* dummy load for compatibility */ + } + } return 0; } @@ -256,8 +260,6 @@ static void piix3_set_irq(void *opaque, int irq_num, int level) int i, pic_irq, pic_level; PIIX3State *piix3 = opaque; - piix3->pci_irq_levels[irq_num] = level; - /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ pic_irq = piix3->dev.config[0x60 + irq_num]; @@ -266,8 +268,9 @@ static void piix3_set_irq(void *opaque, int irq_num, int level) to it */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix3->dev.config[0x60 + i]) - pic_level |= piix3->pci_irq_levels[i]; + if (pic_irq == piix3->dev.config[0x60 + i]) { + pic_level |= pci_bus_get_irq_level(piix3->dev.bus, i); + } } qemu_set_irq(piix3->pic[pic_irq], pic_level); } @@ -309,8 +312,17 @@ static void piix3_reset(void *opaque) pci_conf[0xab] = 0x00; pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; +} - memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels)); +static void piix3_pre_save(void *opaque) +{ + int i; + PIIX3State *piix3 = opaque; + + for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { + piix3->pci_irq_levels_vmstate[i] = + pci_bus_get_irq_level(piix3->dev.bus, i); + } } static const VMStateDescription vmstate_piix3 = { @@ -318,9 +330,11 @@ static const VMStateDescription vmstate_piix3 = { .version_id = 3, .minimum_version_id = 2, .minimum_version_id_old = 2, + .pre_save = piix3_pre_save, .fields = (VMStateField []) { VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + PCI_NUM_PINS, 3), VMSTATE_END_OF_LIST() } };