From patchwork Thu Jul 7 12:37:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 103657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 68823B6F18 for ; Thu, 7 Jul 2011 23:04:10 +1000 (EST) Received: from localhost ([::1]:48215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QeoFO-0006W1-QK for incoming@patchwork.ozlabs.org; Thu, 07 Jul 2011 09:04:03 -0400 Received: from eggs.gnu.org ([140.186.70.92]:45528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qenpp-0000Wf-6q for qemu-devel@nongnu.org; Thu, 07 Jul 2011 08:37:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qenpi-0005Z3-0r for qemu-devel@nongnu.org; Thu, 07 Jul 2011 08:37:37 -0400 Received: from smtp.ispras.ru ([83.149.198.202]:51665) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qenpg-0005YU-Op for qemu-devel@nongnu.org; Thu, 07 Jul 2011 08:37:29 -0400 Received: from ispserv.ispras.ru (ispserv.ispras.ru [83.149.198.72]) by smtp.ispras.ru (Postfix) with ESMTP id A27B75D407E; Thu, 7 Jul 2011 16:30:31 +0400 (MSD) Received: from bulbul.intra.ispras.ru (winnie.ispras.ru [83.149.198.236]) by ispserv.ispras.ru (Postfix) with ESMTP id 5603B3FC50; Thu, 7 Jul 2011 16:37:26 +0400 (MSD) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 7 Jul 2011 16:37:16 +0400 Message-Id: <673a3b026dabb1cf2584388059ce39e8cc3bd9eb.1309865252.git.batuzovk@ispras.ru> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 83.149.198.202 Cc: zhur@ispras.ru Subject: [Qemu-devel] [PATCH v3 5/6] Do constant folding for shift operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations. Signed-off-by: Kirill Batuzov --- tcg/optimize.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c469952..a1bb287 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -102,6 +102,11 @@ static int op_bits(int op) case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: return 32; #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: @@ -111,6 +116,11 @@ static int op_bits(int op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: return 64; #endif default: @@ -205,6 +215,58 @@ static TCGArg do_constant_folding_2(int op, TCGArg x, TCGArg y) CASE_OP_32_64(xor): return x ^ y; + case INDEX_op_shl_i32: + return (uint32_t)x << (uint32_t)y; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_shl_i64: + return (uint64_t)x << (uint64_t)y; +#endif + + case INDEX_op_shr_i32: + return (uint32_t)x >> (uint32_t)y; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_shr_i64: + return (uint64_t)x >> (uint64_t)y; +#endif + + case INDEX_op_sar_i32: + return (int32_t)x >> (int32_t)y; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_sar_i64: + return (int64_t)x >> (int64_t)y; +#endif + + case INDEX_op_rotr_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; +#endif + x = (x << (32 - y)) | (x >> y); + return x; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_rotr_i64: + x = (x << (64 - y)) | (x >> y); + return x; +#endif + + case INDEX_op_rotl_i32: +#if TCG_TARGET_REG_BITS == 64 + x &= 0xffffffff; + y &= 0xffffffff; +#endif + x = (x << y) | (x >> (32 - y)); + return x; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_rotl_i64: + x = (x << y) | (x >> (64 - y)); + return x; +#endif + default: fprintf(stderr, "Unrecognized operation %d in do_constant_folding.\n", op); @@ -278,6 +340,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, switch (op) { CASE_OP_32_64(add): CASE_OP_32_64(sub): + CASE_OP_32_64(shl): + CASE_OP_32_64(shr): + CASE_OP_32_64(sar): + CASE_OP_32_64(rotl): + CASE_OP_32_64(rotr): if (temps[args[1]].state == TCG_TEMP_CONST) { /* Proceed with possible constant folding. */ break; @@ -363,6 +430,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, CASE_OP_32_64(or): CASE_OP_32_64(and): CASE_OP_32_64(xor): + CASE_OP_32_64(shl): + CASE_OP_32_64(shr): + CASE_OP_32_64(sar): + CASE_OP_32_64(rotl): + CASE_OP_32_64(rotr): if (temps[args[1]].state == TCG_TEMP_CONST && temps[args[2]].state == TCG_TEMP_CONST) { gen_opc_buf[op_index] = op_to_movi(op);