From patchwork Fri Nov 26 12:01:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 73167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5CB7BB70D6 for ; Fri, 26 Nov 2010 23:04:21 +1100 (EST) Received: from localhost ([127.0.0.1]:41637 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLx2H-0007cF-JX for incoming@patchwork.ozlabs.org; Fri, 26 Nov 2010 07:04:17 -0500 Received: from [140.186.70.92] (port=57392 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLwzs-000765-8e for qemu-devel@nongnu.org; Fri, 26 Nov 2010 07:01:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PLwzr-0002Ec-09 for qemu-devel@nongnu.org; Fri, 26 Nov 2010 07:01:48 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:52504) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PLwzq-0002EC-FW for qemu-devel@nongnu.org; Fri, 26 Nov 2010 07:01:46 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 4505027EAB; Fri, 26 Nov 2010 21:01:41 +0900 (JST) Received: (nullmailer pid 24344 invoked by uid 1000); Fri, 26 Nov 2010 12:01:41 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Fri, 26 Nov 2010 21:01:41 +0900 Message-Id: <63c89a2034c16abf58608f6db5a1229697813fea.1290772846.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, yamahata@valinux.co.jp, etmartin@cisco.com, wexu2@cisco.com, mst@redhat.com Subject: [Qemu-devel] [PATCH] pci: make command SERR bit writable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org pcie aer wants SERR bit to be writable. So make it writable. For compatibility, introduce compat global property command_serr_enable and don't make it writable when pre 0.14 pc machine. Signed-off-by: Isaku Yamahata --- This patch depends on b1d6dd8ce83e1430b7b0e98c898499a966464227 which is in upstream, but it isn't in pci branch. --- hw/pc_piix.c | 20 ++++++++++++++++++++ hw/pci.c | 5 +++++ hw/pci.h | 4 ++++ 3 files changed, 29 insertions(+), 0 deletions(-) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index e17e878..2994476 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -225,6 +225,14 @@ static QEMUMachine pc_machine_v0_13 = { .desc = "Standard PC", .init = pc_init_pci, .max_cpus = 255, + .compat_props = (GlobalProperty[]) { + { + .driver = "PCI", + .property = "command_serr_enable", + .value = "off", + }, + { /* end of list */ } + } }; static QEMUMachine pc_machine_v0_12 = { @@ -241,6 +249,10 @@ static QEMUMachine pc_machine_v0_12 = { .driver = "virtio-serial-pci", .property = "vectors", .value = stringify(0), + },{ + .driver = "PCI", + .property = "command_serr_enable", + .value = "off", }, { /* end of list */ } } @@ -276,6 +288,10 @@ static QEMUMachine pc_machine_v0_11 = { .driver = "PCI", .property = "rombar", .value = stringify(0), + },{ + .driver = "PCI", + .property = "command_serr_enable", + .value = "off", }, { /* end of list */ } } @@ -323,6 +339,10 @@ static QEMUMachine pc_machine_v0_10 = { .driver = "PCI", .property = "rombar", .value = stringify(0), + },{ + .driver = "PCI", + .property = "command_serr_enable", + .value = "off", }, { /* end of list */ } }, diff --git a/hw/pci.c b/hw/pci.c index d02f980..6b7e63c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -57,6 +57,8 @@ struct BusInfo pci_bus_info = { DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), + DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, + QEMU_PCI_CAP_SERR_BITNR, true), DEFINE_PROP_END_OF_LIST() } }; @@ -568,6 +570,9 @@ static void pci_init_wmask(PCIDevice *dev) pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INTX_DISABLE); + if (dev->cap_present & QEMU_PCI_CAP_SERR) { + pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); + } memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, config_size - PCI_CONFIG_HEADER_SIZE); diff --git a/hw/pci.h b/hw/pci.h index 89f7b76..e20ac36 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -118,6 +118,10 @@ enum { /* multifunction capable device */ #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), + + /* enable comman register SERR bit */ +#define QEMU_PCI_CAP_SERR_BITNR 4 + QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), }; struct PCIDevice {