From patchwork Tue Jun 17 04:18:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 360310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CA43D140087 for ; Tue, 17 Jun 2014 14:19:02 +1000 (EST) Received: from localhost ([::1]:47289 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WwkrM-0007jj-N3 for incoming@patchwork.ozlabs.org; Tue, 17 Jun 2014 00:19:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50038) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwkqw-00073S-Nl for qemu-devel@nongnu.org; Tue, 17 Jun 2014 00:18:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wwkqq-0001Qw-Pm for qemu-devel@nongnu.org; Tue, 17 Jun 2014 00:18:34 -0400 Received: from mail-pd0-x232.google.com ([2607:f8b0:400e:c02::232]:48205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwkqq-0001Qq-Fu for qemu-devel@nongnu.org; Tue, 17 Jun 2014 00:18:28 -0400 Received: by mail-pd0-f178.google.com with SMTP id r10so5114806pdi.23 for ; Mon, 16 Jun 2014 21:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=W78e4gQm0EuxS/y+Wf5eNkyP2vOCOr1YN0gZo7/+EII=; b=oCeUNIZUuJusKebur2xqAnBdQQjUDqpmGJt8ehFu3wxiGjfDn05101MgFi3p7UbXhk HmWIUq/DZx1pquCj2/J0Z5+jcu0ig+/bt4D8lnYQS2nXpm+3owkerrxaBsgEelk9tRSI i+d7Pe7ltsIGABg4DzVmmuXnazlm375e1T7TmDAE+ZOU6dVhvac0AgIskUExLA8VLNMo +mrskbKLHS2sM0Iq8Hc8PIYRURBHUSTWEz6PMb390M3cO8GO5pfxMBfxw5Wqikm67979 UTrDWBuIKqi0yP6TbohbUs2YytLiVHWsMFabSGDQ9bZehEZiJREn5EivnMLVskp9BWYu AMQw== X-Received: by 10.68.161.101 with SMTP id xr5mr9524610pbb.168.1402978707627; Mon, 16 Jun 2014 21:18:27 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ln2sm78419453pab.35.2014.06.16.21.18.24 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 16 Jun 2014 21:18:27 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Tue, 17 Jun 2014 14:18:21 +1000 Message-Id: <622632d97d08b9609a5d2125b5686454fa939a8f.1402978426.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <4823e5afcfda6eb72c4479f8f4243bbe498551c1.1402978426.git.alistair.francis@xilinx.com> References: <4823e5afcfda6eb72c4479f8f4243bbe498551c1.1402978426.git.alistair.francis@xilinx.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::232 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [RFC v2 2/2] zynq: Update Zynq to init the CPU in the a9mpcore device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch removes the initialisation of the ARM Cortex-A9 in Zynq and instead allows the a9mpcore device to init the CPU. This also updates components that rely on the CPU and GIC, as they are now initialised in a slightly different way Signed-off-by: Alistair Francis --- V2: - Small changes based on comments from Peter Crosthwaite - Updates to be compatible with the new MPCore implementation V1: Initial Release hw/arm/xilinx_zynq.c | 47 ++++++++++++++++------------------------------- 1 files changed, 16 insertions(+), 31 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index ba5aa82..f5de2d8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -26,6 +26,7 @@ #include "hw/loader.h" #include "hw/ssi.h" #include "qemu/error-report.h" +#include "hw/cpu/a9mpcore.h" #define NUM_SPI_FLASHES 4 #define NUM_QSPI_FLASHES 2 @@ -104,12 +105,10 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, static void zynq_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ObjectClass *cpu_oc; - ARMCPU *cpu; + A9MPPrivState *mpcore; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); @@ -119,27 +118,8 @@ static void zynq_init(MachineState *machine) Error *err = NULL; int n; - if (!cpu_model) { - cpu_model = "cortex-a9"; - } - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); - - object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err); - if (err) { - error_report("%s", error_get_pretty(err)); - exit(1); - } - - object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); - if (err) { - error_report("%s", error_get_pretty(err)); - exit(1); - } - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - if (err) { - error_report("%s", error_get_pretty(err)); + if (machine->cpu_model) { + error_report("Zynq does not support CPU model override!\n"); exit(1); } @@ -171,16 +151,21 @@ static void zynq_init(MachineState *machine) qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); - dev = qdev_create(NULL, "a9mpcore_priv"); - qdev_prop_set_uint32(dev, "num-cpu", 1); - qdev_init_nofail(dev); - busdev = SYS_BUS_DEVICE(dev); + mpcore = A9MPCORE_PRIV(object_new("a9mpcore_priv")); + qdev_prop_set_uint32(DEVICE(mpcore), "num-cpu", 1); + qdev_prop_set_uint32(DEVICE(mpcore), "midr", ZYNQ_BOARD_MIDR); + qdev_prop_set_uint64(DEVICE(mpcore), "reset-cbar", MPCORE_PERIPHBASE); + object_property_set_bool(OBJECT(mpcore), true, "realized", &err); + if (err != NULL) { + error_report("Couldn't realize the Zynq A9MPCore: %s", + error_get_pretty(err)); + exit(1); + } + busdev = SYS_BUS_DEVICE(DEVICE(mpcore)); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); - sysbus_connect_irq(busdev, 0, - qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); for (n = 0; n < 64; n++) { - pic[n] = qdev_get_gpio_in(dev, n); + pic[n] = qdev_get_gpio_in(DEVICE(mpcore), n); } zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);