From patchwork Sat Dec 19 22:32:13 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 41480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 34A29B6F0C for ; Sun, 20 Dec 2009 09:36:39 +1100 (EST) Received: from localhost ([127.0.0.1]:39536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM7ue-0007IA-GQ for incoming@patchwork.ozlabs.org; Sat, 19 Dec 2009 17:36:36 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NM7rN-0006Or-I4 for qemu-devel@nongnu.org; Sat, 19 Dec 2009 17:33:13 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NM7rM-0006OB-Av for qemu-devel@nongnu.org; Sat, 19 Dec 2009 17:33:12 -0500 Received: from [199.232.76.173] (port=52271 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NM7rM-0006O8-8m for qemu-devel@nongnu.org; Sat, 19 Dec 2009 17:33:12 -0500 Received: from are.twiddle.net ([75.149.56.221]:37007) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NM7rL-0007E9-7k for qemu-devel@nongnu.org; Sat, 19 Dec 2009 17:33:12 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 7E915A32; Sat, 19 Dec 2009 14:33:09 -0800 (PST) Message-Id: <5cea73f33cd1e571983c0fd607fb5a3be45e2e39.1261260692.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Sat Dec 19 14:32:13 PST 2009 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH 3/3] tcg-mips: Implement movcond. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org --- tcg/mips/tcg-target.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 117 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 2a2913d..123a7af 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -297,6 +297,8 @@ enum { OPC_SRAV = OPC_SPECIAL | 0x07, OPC_JR = OPC_SPECIAL | 0x08, OPC_JALR = OPC_SPECIAL | 0x09, + OPC_MOVZ = OPC_SPECIAL | 0x0A, + OPC_MOVN = OPC_SPECIAL | 0x0B, OPC_MFHI = OPC_SPECIAL | 0x10, OPC_MFLO = OPC_SPECIAL | 0x12, OPC_MULT = OPC_SPECIAL | 0x18, @@ -464,8 +466,8 @@ static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) } } -static void tcg_out_brcond(TCGContext *s, int cond, int arg1, - int arg2, int label_index) +static void tcg_out_brcond_nodelay(TCGContext *s, int cond, int arg1, + int arg2, int label_index) { TCGLabel *l = &s->labels[label_index]; @@ -517,6 +519,12 @@ static void tcg_out_brcond(TCGContext *s, int cond, int arg1, } else { tcg_out_reloc(s, s->code_ptr - 4, R_MIPS_PC16, label_index, 0); } +} + +static void tcg_out_brcond(TCGContext *s, int cond, int arg1, + int arg2, int label_index) +{ + tcg_out_brcond_nodelay(s, cond, arg1, arg2, label_index); tcg_out_nop(s); } @@ -749,6 +757,108 @@ static void tcg_out_setcond2(TCGContext *s, int cond, int dest, } } +static inline int have_movz(void) +{ + /* ??? It's unclear what we want to do with different mips isa's. + We appear to already be assuming HILO interlocks on the MUL/DIV + instructions, which (according to gcc) implies MIPS{32,64} plus + the r5500. All of these also have MUL3, which would elide the + use of the LO register for simple multiply. MIPS{4,32,64} have + the conditional moves, but the r5500 doesn't. */ +#if defined(__mips) && __mips >= 32 + /* Use MOVZ on MIPS{32,64}. */ + return 1; +#else + /* Mips has no architected cpuid. We could probably look at + /proc/cpuinfo or similar to figure out what's running. */ + return 0; +#endif +} + +static void tcg_out_movcond(TCGContext *s, int cond, int dest, + int c1, int c2, int c2const, int vt, int vf) +{ + int condr; + + if (vt == vf) { + tcg_out_mov(s, dest, vt); + return; + } + + if (dest == vt) { + vt = vf, vf = dest; + cond = tcg_invert_cond(cond); + } + + condr = TCG_COND_NE; + switch (cond) { + case TCG_COND_EQ: + condr = TCG_COND_EQ; + /* FALLTHRU */ + case TCG_COND_NE: + if (c2 != 0) { + if (c2const) + tcg_out_opc_imm(s, OPC_XORI, TCG_REG_T0, c1, c2); + else + tcg_out_opc_reg(s, OPC_XOR, TCG_REG_T0, c1, c2); + c1 = TCG_REG_T0; + } + break; + + case TCG_COND_LE: + case TCG_COND_LEU: + if (c2const && c2 < 32767) { + c2++; + cond = (cond == TCG_COND_LE ? TCG_COND_LT : TCG_COND_LTU); + goto do_setcond; + } + /* FALLTHRU */ + + case TCG_COND_GE: + case TCG_COND_GEU: + cond = tcg_invert_cond(cond); + condr = TCG_COND_EQ; + /* FALLTHRU */ + + case TCG_COND_LT: + case TCG_COND_LTU: + case TCG_COND_GT: + case TCG_COND_GTU: + do_setcond: + tcg_out_setcond(s, cond, TCG_REG_T0, c1, c2, c2const); + c1 = TCG_REG_T0; + break; + + default: + tcg_abort(); + } + + if (have_movz()) { + if (dest != vf) { + if (dest == c1) { + tcg_out_mov(s, TCG_REG_AT, c1); + c1 = TCG_REG_AT; + } + tcg_out_mov(s, dest, vf); + } + tcg_out_opc_reg(s, (condr == TCG_COND_NE ? OPC_MOVN : OPC_MOVZ), + dest, vt, c1); + } else { + int label_over = gen_new_label(); + + tcg_out_brcond_nodelay(s, tcg_invert_cond(condr), + c1, TCG_REG_ZERO, label_over); + if (dest != vf) { + tcg_out_mov(s, dest, vf); + } else { + tcg_out_nop(s); + } + + tcg_out_mov(s, dest, vt); + tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr); + } +} + #if defined(CONFIG_SOFTMMU) #include "../../softmmu_defs.h" @@ -1328,6 +1438,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4], const_args[3], const_args[4]); break; + case INDEX_OP_movcond_i32: + tcg_out_movcond(s, args[5], args[0], args[1], args[2], const_args[2], + args[3], args[4]); + break; case INDEX_op_qemu_ld8u: tcg_out_qemu_ld(s, args, 0); @@ -1409,6 +1523,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_setcond_i32, { "r", "r", "rJ" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } }, + { INDEX_op_movcond_i32, { "r", "r", "rJ", "rZ", "rZ" } }, #if TARGET_LONG_BITS == 32 { INDEX_op_qemu_ld8u, { "L", "lZ" } },