From patchwork Wed Feb 19 23:57:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 322035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D62A62C009E for ; Thu, 20 Feb 2014 10:57:45 +1100 (EST) Received: from localhost ([::1]:34601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGH1L-0005Qg-7c for incoming@patchwork.ozlabs.org; Wed, 19 Feb 2014 18:57:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGH10-00059M-7z for qemu-devel@nongnu.org; Wed, 19 Feb 2014 18:57:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WGH0u-0004t2-CL for qemu-devel@nongnu.org; Wed, 19 Feb 2014 18:57:22 -0500 Received: from mail-qc0-x22a.google.com ([2607:f8b0:400d:c01::22a]:53184) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WGH0u-0004sy-5t for qemu-devel@nongnu.org; Wed, 19 Feb 2014 18:57:16 -0500 Received: by mail-qc0-f170.google.com with SMTP id c9so1713316qcz.15 for ; Wed, 19 Feb 2014 15:57:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=vaW5UFkMv31jKzz2SSSPFlhFSckU5kzPF8bDp/qC0Vg=; b=XzfCS+dtIRzR9jqwg6FfGnYs+LH5YDqNOucFKX15cO8fXz8aquO33ioF8Iaxlow9HM Pc1XvKJcPBpSOr2oscrJDAY60dIbz+jSMvKuXDes01yla3IPAndM7vQgBdqWTWPRk8FE zroz9f7CqjrcyXrrigqZTSOhKFzNGwnryBGjVAixCfJNY+6GU2FYdL3/FVY/t0AtLz5w nZVKtWG8eG42Fqh/qkQC311saW22dJGXk3XbA1Fh44FpS8hHTErVg8BdgAXLwU2tL04G eXW/OevFb/cx2I8yeg98vB3I1LD0EVsrjwiXnnKlKvyZ0WWrBVdF76lxGOYuVsltq1TS dn6w== X-Received: by 10.140.105.35 with SMTP id b32mr52402662qgf.36.1392854235697; Wed, 19 Feb 2014 15:57:15 -0800 (PST) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id k32sm4159713qgf.18.2014.02.19.15.57.14 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 19 Feb 2014 15:57:15 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Thu, 20 Feb 2014 09:57:11 +1000 Message-Id: <57a391d51a6430e74fad5b88316c504b9217c306.1392853953.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22a Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v7 1/1] target-arm: Implements the ARM PMCCNTR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis --- V7: Fixed a bug that caused the cycle count scaling to be determined by the PMCRDP register instead of PMCRD. Also stopped PMCRDP from disabling the counter. Thanks to Peter Maydell V6: Rebase to include Peter Maydell's 'Convert performance monitor reginfo to accesfn' patch. Remove the raw_fn's as the read/write functions already do what is required. V5: Implement the actual write function to make sure that migration works correctly. Also includes the raw_read/write as the normal read/write functions depend on the pmcr register. So they don't allow for the pmccntr register to be written first. V4: Some bug fixes pointed out by Peter Crosthwaite. Including increasing the accuracy of the timer. V3: Fixed up incorrect reset, disable and enable handling that was submitted in V2. The patch should now also handle changing of the clock scaling. V2: Incorporated the comments that Peter Maydell and Peter Crosthwaite had. Now the implementation only requires one CPU state target-arm/cpu.h | 4 ++ target-arm/helper.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3c8a2db..14fd1ae 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -215,6 +215,10 @@ typedef struct CPUARMState { uint32_t c15_diagnostic; /* diagnostic register */ uint32_t c15_power_diagnostic; uint32_t c15_power_control; /* power control */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value + */ + uint32_t c15_ccnt; } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index b547f04..a5f4770 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,6 +13,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, target_ulong *page_size); #endif +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -478,9 +483,37 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + uint32_t temp_ticks; + + temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRE) { + /* If the counter is enabled */ + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; + } else { + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } + } + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + if (env->cp15.c9_pmcr & PMCRE) { + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /= 64; + } + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } } static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -536,6 +569,46 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.c12_vbar = value & ~0x1Ful; } +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + return env->cp15.c15_ccnt; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + return total_ticks - env->cp15.c15_ccnt; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, set the absolute value */ + env->cp15.c15_ccnt = value; + return; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + env->cp15.c15_ccnt = total_ticks - value; +} + static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -595,9 +668,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, .accessfn = pmreg_access }, - /* Unimplemented, RAZ/WI. */ { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, + .readfn = pmccntr_read, .writefn = pmccntr_write, .accessfn = pmreg_access }, { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW,