From patchwork Wed Mar 12 21:26:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier DANET X-Patchwork-Id: 329718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 256C82C0090 for ; Thu, 13 Mar 2014 08:57:25 +1100 (EST) Received: from localhost ([::1]:34984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNqec-0001DN-Pb for incoming@patchwork.ozlabs.org; Wed, 12 Mar 2014 17:25:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNqe6-0000za-8z for qemu-devel@nongnu.org; Wed, 12 Mar 2014 17:25:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WNqe0-0004W9-4G for qemu-devel@nongnu.org; Wed, 12 Mar 2014 17:25:02 -0400 Received: from mout.gmx.net ([212.227.17.20]:57633) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNqdz-0004W4-PH for qemu-devel@nongnu.org; Wed, 12 Mar 2014 17:24:56 -0400 Received: from [192.168.1.24] ([92.156.90.121]) by mail.gmx.com (mrgmx102) with ESMTPSA (Nemesis) id 0MHrk1-1WRR8o40oH-003alG; Wed, 12 Mar 2014 22:24:44 +0100 Message-ID: <5320D11F.3060703@caramail.com> Date: Wed, 12 Mar 2014 22:26:55 +0100 From: Olivier Danet User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: qemu-devel , Blue Swirl , Mark Cave-Ayland X-Provags-ID: V03:K0:L8xmHVZ82+UhlOaPztCOPGFJczAEJQrPVIDJBjVEubCkLmcr1jd 6DtLcBy9xnnYj+EiFveBe38n8z/RED2h9YIqRp1Ir2QmMi/4E5N5Hepe9+rlQcTdIDQChPh 58HRnRrimZmW0FqCBVmcW3eK72TYhvcnA92fGM3UXqefxFHDFOu0n3COsQXVG8HXbXdYkkI k56sU2vuGTAssguv7H9+Q== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 212.227.17.20 Subject: [Qemu-devel] [PATCH] sparc32 : Signed integer division overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I wanted to test an integer divider for SPARC32, and tried the stress test program on QEMU, which choked on the division -0x8000_0000_0000_0000 / -1 (QEMU compiled on x86_64). Excerpt from the test program : ------------------------------------------------------------------- #include typedef unsigned uint32; typedef unsigned long long uint64; typedef signed int32; typedef signed long long int64; void sdiv(int64 x, int32 y, int32 *q, uint32 *ov) { uint32 a,b,c,d,e; a=x>>32; b=x; c=y; __asm__ __volatile__("wr %2,%%y\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "sdivcc %3,%4,%0\n\t" "or %%r0,0,%1\n\t" "bvc xxa\n\t" "nop\n\t" "add %1,1,%1\n\t" "xxa:bpos xxb\n\t" "nop\n\t" "add %1,2,%1\n\t" "xxb:bne xxc\n\t" "nop\n\t" "add %1,4,%1\n\t" "xxc:nop\n\t" : "=r"(d),"=r"(e):"r"(a),"r"(b),"r"(c) ); *q=d; *ov=e & 1; } void main(void) { uint64 x; uint32 y; int32 q; int32 ov; x = 1LL << 63; y = -1; sdiv(x, y, &q, &ov); } Here is a patch for handling this corner case on SPARC32. SPARC64 division already checks this in helper_sdivx(), some other architectures seem to do the same (for example, target-arm/helper.c: HELPER(sdiv)) env->cc_src2 = overflow; ------------------------------------------------------------------- =================================================================== The integer division 0x8000_0000_0000_0000 / -1 must be handled separately to avoid overflows on the QEMU host. Signed-off-by: Olivier Danet ------------------------------------------------------------------- diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 57c20af..b6b5937 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -116,14 +116,16 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, if (x1 == 0) { cpu_restore_state(env, GETPC()); helper_raise_exception(env, TT_DIV_ZERO); - } - - x0 = x0 / x1; - if ((int32_t) x0 != x0) { - x0 = x0 < 0 ? 0x80000000 : 0x7fffffff; + } else if (x1 == -1 && x0 == 0x8000000000000000) { + x0 = 0x7fffffff; overflow = 1; + } else { + x0 = x0 / x1; + if ((int32_t) x0 != x0) { + x0 = x0 < 0 ? 0x80000000 : 0x7fffffff; + overflow = 1; + } } - if (cc) { env->cc_dst = x0;