| Message ID | 4cdbb66fc918f00f51e6fb6266e1b0714496b266.1716763435.git.balaton@eik.bme.hu |
|---|---|
| State | New |
| Headers | show |
| Series | Remaining MMU clean up patches | expand |
On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > This function takes PowerPCCPU but only needs the env from it. Change > its parameter to CPUPPCState *env. Acked-by: Nicholas Piggin <npiggin@gmail.com> > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > hw/ppc/spapr_rtas.c | 2 +- > target/ppc/mmu-book3s-v3.h | 4 ++-- > target/ppc/mmu_common.c | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index f329693c55..38e94fc0d7 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -177,7 +177,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, > * New cpus are expected to start in the same radix/hash mode > * as the existing CPUs > */ > - if (ppc64_v3_radix(callcpu)) { > + if (ppc64_v3_radix(&callcpu->env)) { > lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; > } else { > lpcr &= ~(LPCR_UPRT | LPCR_GTSE | LPCR_HR); > diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h > index be66e26604..e52129ff7f 100644 > --- a/target/ppc/mmu-book3s-v3.h > +++ b/target/ppc/mmu-book3s-v3.h > @@ -75,9 +75,9 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, > * dig out the partition table in the fast path. This is > * also how the HW uses it. > */ > -static inline bool ppc64_v3_radix(PowerPCCPU *cpu) > +static inline bool ppc64_v3_radix(CPUPPCState *env) > { > - return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR); > + return !!(env->spr[SPR_LPCR] & LPCR_HR); > } > > #endif /* TARGET_PPC64 */ > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index b45eb64f6e..ab055ca96b 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -565,7 +565,7 @@ void dump_mmu(CPUPPCState *env) > dump_slb(env_archcpu(env)); > break; > case POWERPC_MMU_3_00: > - if (ppc64_v3_radix(env_archcpu(env))) { > + if (ppc64_v3_radix(env)) { > qemu_log_mask(LOG_UNIMP, "%s: the PPC64 MMU is unsupported\n", > __func__); > } else { > @@ -810,7 +810,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, > switch (cpu->env.mmu_model) { > #if defined(TARGET_PPC64) > case POWERPC_MMU_3_00: > - if (ppc64_v3_radix(cpu)) { > + if (ppc64_v3_radix(&cpu->env)) { > return ppc_radix64_xlate(cpu, eaddr, access_type, raddrp, > psizep, protp, mmu_idx, guest_visible); > }
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index f329693c55..38e94fc0d7 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -177,7 +177,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, * New cpus are expected to start in the same radix/hash mode * as the existing CPUs */ - if (ppc64_v3_radix(callcpu)) { + if (ppc64_v3_radix(&callcpu->env)) { lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; } else { lpcr &= ~(LPCR_UPRT | LPCR_GTSE | LPCR_HR); diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h index be66e26604..e52129ff7f 100644 --- a/target/ppc/mmu-book3s-v3.h +++ b/target/ppc/mmu-book3s-v3.h @@ -75,9 +75,9 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, * dig out the partition table in the fast path. This is * also how the HW uses it. */ -static inline bool ppc64_v3_radix(PowerPCCPU *cpu) +static inline bool ppc64_v3_radix(CPUPPCState *env) { - return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR); + return !!(env->spr[SPR_LPCR] & LPCR_HR); } #endif /* TARGET_PPC64 */ diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index b45eb64f6e..ab055ca96b 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -565,7 +565,7 @@ void dump_mmu(CPUPPCState *env) dump_slb(env_archcpu(env)); break; case POWERPC_MMU_3_00: - if (ppc64_v3_radix(env_archcpu(env))) { + if (ppc64_v3_radix(env)) { qemu_log_mask(LOG_UNIMP, "%s: the PPC64 MMU is unsupported\n", __func__); } else { @@ -810,7 +810,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, switch (cpu->env.mmu_model) { #if defined(TARGET_PPC64) case POWERPC_MMU_3_00: - if (ppc64_v3_radix(cpu)) { + if (ppc64_v3_radix(&cpu->env)) { return ppc_radix64_xlate(cpu, eaddr, access_type, raddrp, psizep, protp, mmu_idx, guest_visible); }
This function takes PowerPCCPU but only needs the env from it. Change its parameter to CPUPPCState *env. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- hw/ppc/spapr_rtas.c | 2 +- target/ppc/mmu-book3s-v3.h | 4 ++-- target/ppc/mmu_common.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)