From patchwork Tue Dec 20 19:10:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 132501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 52FEAB7056 for ; Wed, 21 Dec 2011 06:11:10 +1100 (EST) Received: from localhost ([::1]:60708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd55b-00040J-6A for incoming@patchwork.ozlabs.org; Tue, 20 Dec 2011 14:11:03 -0500 Received: from eggs.gnu.org ([140.186.70.92]:47044) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd559-000323-6s for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:10:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rd557-0005sH-R1 for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:10:35 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:58265) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd557-0005sC-Kx for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:10:33 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp19.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 0327B3C86DC; Tue, 20 Dec 2011 14:10:33 -0500 (EST) X-Virus-Scanned: OK Received: by smtp19.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id D11883C86D4; Tue, 20 Dec 2011 14:10:32 -0500 (EST) Message-ID: <4EF0DDAB.2030905@calxeda.com> Date: Tue, 20 Dec 2011 13:10:35 -0600 From: Mark Langsdorf User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: qemu-devel@nongnu.org, paul@codesourcery.com, peter.maydell@linaro.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 67.192.241.191 Subject: [Qemu-devel] [PATCH 1/9] arm: add missing scu registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Rob Herring Add power control and non-secure access ctrl registers Signed-off-by: Rob Herring Signed-off-by: Mark Langsdorf --- hw/a9mpcore.c | 26 ++++++++++++++++++++++++-- 1 files changed, 24 insertions(+), 2 deletions(-) case 0x40: /* Filtering Start Address Register */ @@ -73,6 +80,22 @@ static void a9_scu_write(void *opaque, target_phys_addr_t offset, break; case 0x4: /* Configuration: RO */ break; + case 0x08: /* Power Control */ + s->scu_status &= ~0xff; + s->scu_status |= value & 0xff; + break; + case 0x09: /* Power Control */ + s->scu_status &= ~(0xff << 8); + s->scu_status |= (value & 0xff) << 8; + break; + case 0x0A: /* Power Control */ + s->scu_status &= ~(0xff << 16); + s->scu_status |= (value & 0xff) << 16; + break; + case 0x0B: /* Power Control */ + s->scu_status &= ~(0xff << 24); + s->scu_status |= (value & 0xff) << 24; + break; case 0x0c: /* Invalidate All Registers In Secure State */ /* no-op as we do not implement caches */ break; @@ -80,7 +103,6 @@ static void a9_scu_write(void *opaque, target_phys_addr_t offset, case 0x44: /* Filtering End Address Register */ /* RAZ/WI, like an implementation with only one AXI master */ break; - case 0x8: /* CPU Power Status */ case 0x50: /* SCU Access Control Register */ case 0x54: /* SCU Non-secure Access Control Register */ /* unimplemented, fall through */ diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index cd2985f..6e03fad 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -29,6 +29,7 @@ gic_get_current_cpu(void) typedef struct a9mp_priv_state { gic_state gic; uint32_t scu_control; + uint32_t scu_status; uint32_t old_timer_status[8]; uint32_t num_cpu; qemu_irq *timer_irq; @@ -48,7 +49,13 @@ static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset, case 0x04: /* Configuration */ return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); case 0x08: /* CPU Power Status */ - return 0; + return s->scu_status; + case 0x09: /* CPU status. */ + return s->scu_status >> 8; + case 0x0a: /* CPU status. */ + return s->scu_status >> 16; + case 0x0b: /* CPU status. */ + return s->scu_status >> 24; case 0x0c: /* Invalidate All Registers In Secure State */ return 0;