@@ -193,11 +193,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
break;
- case 'c':
- /* millicode division return register. */
- ct->ct | TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 1u << TCG_REG_RET1);
- break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
@@ -680,65 +675,6 @@ static void tcg_out_xmpyu(TCGContext *s, int retl, int reth,
}
}
-/* We define the following table directly in assembly so that we
- can avoid getting PLABEL addresses. */
-
-extern tcg_target_long qemu_milli[4];
-asm(".section .rodata\n\
- .import $$divI,millicode\n\
- .import $$remI,millicode\n\
- .import $$divU,millicode\n\
- .import $$remU,millicode\n\
- .type qemu_milli,@object\n\
- .size qemu_milli,16\n\
-qemu_milli:\n\
- .word $$divI\n\
- .word $$remI\n\
- .word $$divU\n\
- .word $$remU\n\
- .previous");
-
-#define MILLI_DIVI 0
-#define MILLI_REMI 1
-#define MILLI_DIVU 2
-#define MILLI_REMU 3
-
-/* ??? Move this up in tcg.c. */
-static void tcg_reg_free(TCGContext *, int);
-
-/* Note that the return is constrained to be r29, and the inputs are
- constrained to not be in the first two parameter registers. Otherwise,
- we clobber r1 and r31, which are already marked as reserved. */
-static void tcg_out_milli(TCGContext *s, int arg1, int arg2, int which)
-{
- tcg_target_long routine, disp;
-
- /* The parameter registers are clobbered. Store them back to their
- stack slots before we lose the contents. */
- tcg_reg_free(s, TCG_REG_R26);
- tcg_reg_free(s, TCG_REG_R25);
- tcg_out_mov(s, TCG_REG_R26, arg1);
-
- routine = qemu_milli[which];
- disp = (routine - ((tcg_target_long)s->code_ptr + 8)) >> 2;
-
- if (check_fit_tl(disp, 17)) {
- tcg_out32(s, INSN_BL | INSN_R2(TCG_REG_R31) | reassemble_17(disp));
- } else {
- uint32_t hi, lo;
-
- hi = routine >> 11;
- lo = routine & 0x7ff;
-
- tcg_out32(s, INSN_LDIL | INSN_R2(TCG_REG_R1) | reassemble_21(hi));
- tcg_out32(s, INSN_BLE_SR4 | INSN_R2(TCG_REG_R1)
- | reassemble_17(lo >> 2));
- }
-
- /* Second input copy in call delay slot. */
- tcg_out_mov(s, TCG_REG_R25, arg2);
-}
-
static void tcg_out_branch(TCGContext *s, int label_index, int nul)
{
TCGLabel *l = &s->labels[label_index];
@@ -1443,19 +1379,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_xmpyu(s, args[0], args[1], args[2], args[3]);
break;
- case INDEX_op_div_i32:
- tcg_out_milli(s, args[1], args[2], MILLI_DIVI);
- break;
- case INDEX_op_divu_i32:
- tcg_out_milli(s, args[1], args[2], MILLI_DIVU);
- break;
- case INDEX_op_rem_i32:
- tcg_out_milli(s, args[1], args[2], MILLI_REMI);
- break;
- case INDEX_op_remu_i32:
- tcg_out_milli(s, args[1], args[2], MILLI_REMU);
- break;
-
case INDEX_op_bswap16_i32:
tcg_out_bswap16(s, args[0], args[1], 0);
break;
@@ -1590,11 +1513,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
- { INDEX_op_div_i32, { "c", "L", "L" } },
- { INDEX_op_divu_i32, { "c", "L", "L" } },
- { INDEX_op_rem_i32, { "c", "L", "L" } },
- { INDEX_op_remu_i32, { "c", "L", "L" } },
-
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
@@ -82,7 +82,7 @@ enum {
#define TCG_TARGET_STACK_GROWSUP
/* optional instructions */
-#define TCG_TARGET_HAS_div_i32
+// #define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32