| Message ID | 4831384.GXAFRqVoOG@linux-e202.suse.de |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/boot: Set SCR_EL3.FGTEn when booting kernel | expand |
On Wed, 13 Sept 2023 at 12:58, Fabian Vogt <fvogt@suse.de> wrote: > > Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit > handles SCR_EL3.FGTEn for FEAT_FGT: > > When we direct boot a kernel on a CPU which emulates EL3, we need to > set up the EL3 system registers as the Linux kernel documentation > specifies: > https://www.kernel.org/doc/Documentation/arm64/booting.rst > > > For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: > > - If EL3 is present and the kernel is entered at EL2: > > - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. > > Signed-off-by: Fabian Vogt <fvogt@suse.de> > --- Applied to target-arm.next, thanks. (We seem to have a habit of forgetting these...) -- PMM
13.09.2023 14:57, Fabian Vogt : > Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit > handles SCR_EL3.FGTEn for FEAT_FGT: > > When we direct boot a kernel on a CPU which emulates EL3, we need to > set up the EL3 system registers as the Linux kernel documentation > specifies: > https://www.kernel.org/doc/Documentation/arm64/booting.rst > >> For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: >> - If EL3 is present and the kernel is entered at EL2: >> - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. Am I right assuming this makes no sense to pick up for stable-7.2 since it doesn't even have aa64_fgt definitions (commit 15126d9ce2 "target/arm: Define the FEAT_FGT registers"), or should this commit be picked up too? This and subsequent change in this area, "target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0" Thanks, /mjt
On Sat, 21 Oct 2023 at 13:30, Michael Tokarev <mjt@tls.msk.ru> wrote: > > 13.09.2023 14:57, Fabian Vogt : > > Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit > > handles SCR_EL3.FGTEn for FEAT_FGT: > > > > When we direct boot a kernel on a CPU which emulates EL3, we need to > > set up the EL3 system registers as the Linux kernel documentation > > specifies: > > https://www.kernel.org/doc/Documentation/arm64/booting.rst > > > >> For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: > >> - If EL3 is present and the kernel is entered at EL2: > >> - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. > > Am I right assuming this makes no sense to pick up for stable-7.2 since > it doesn't even have aa64_fgt definitions (commit 15126d9ce2 > "target/arm: Define the FEAT_FGT registers"), or should this commit > be picked up too? Correct. stable-7.2 doesn't implement FEAT_FGT, so it doesn't need this fix for that feature's implementation. > This and subsequent change in this area, "target/arm: Fix CNTPCT_EL0 > trapping from EL0 when HCR_EL2.E2H is 0" That's a safe bugfix back to any QEMU that has the code that it's patching, but it's also not super high priority, since the code has been that way since 2020 and we only just noticed :-) (Affects running Xen in emulation under QEMU.) thanks -- PMM
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 720f22531a..24fa169060 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,6 +761,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_hcx, cpu)) { env->cp15.scr_el3 |= SCR_HXEN; } + if (cpu_isar_feature(aa64_fgt, cpu)) { + env->cp15.scr_el3 |= SCR_FGTEN; + } + /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently:
Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit handles SCR_EL3.FGTEn for FEAT_FGT: When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst > For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: > - If EL3 is present and the kernel is entered at EL2: > - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. Signed-off-by: Fabian Vogt <fvogt@suse.de> --- hw/arm/boot.c | 4 ++++ 1 file changed, 4 insertions(+)