From patchwork Fri Jun 15 09:47:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 165074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 20B64B705E for ; Fri, 15 Jun 2012 19:51:22 +1000 (EST) Received: from localhost ([::1]:42940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTBX-0000KN-Vx for incoming@patchwork.ozlabs.org; Fri, 15 Jun 2012 05:51:19 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTBB-00087p-3m for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:51:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SfTB6-0001Fp-1F for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:50:56 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:52971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfTB5-0001F9-7h for qemu-devel@nongnu.org; Fri, 15 Jun 2012 05:50:51 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q5FAQ7wd006953; Fri, 15 Jun 2012 18:26:07 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 339E2146052B; Fri, 15 Jun 2012 17:47:58 +0800 (CST) From: Guan Xuetao To: qemu-devel@nongnu.org Date: Fri, 15 Jun 2012 17:47:43 +0800 Message-Id: <46e13cbfe6510815e1b5b34049f41fa8434387a2.1339753406.git.gxt@mprc.pku.edu.cn> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, Guan Xuetao , afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv2 10/13] unicore32-softmmu: Add puv3 pm support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds puv3 pm (power management) support, include pm device simulation for kernel booting. Signed-off-by: Guan Xuetao --- Makefile.objs | 1 + hw/puv3.c | 1 + hw/puv3_pm.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+), 0 deletions(-) create mode 100644 hw/puv3_pm.c diff --git a/Makefile.objs b/Makefile.objs index d7c63c4..d14a08e 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -278,6 +278,7 @@ hw-obj-$(CONFIG_JAZZ_LED) += jazz_led.o hw-obj-$(CONFIG_PUV3) += puv3_intc.o hw-obj-$(CONFIG_PUV3) += puv3_ost.o hw-obj-$(CONFIG_PUV3) += puv3_gpio.o +hw-obj-$(CONFIG_PUV3) += puv3_pm.o # PCI watchdog devices hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o diff --git a/hw/puv3.c b/hw/puv3.c index 453b404..595aa9e 100644 --- a/hw/puv3.c +++ b/hw/puv3.c @@ -48,6 +48,7 @@ static void puv3_soc_init(CPUUniCore32State *env) } /* Initialize minimal necessary devices for kernel booting */ + sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL); sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]); sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE, irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1], diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c new file mode 100644 index 0000000..d3b646c --- /dev/null +++ b/hw/puv3_pm.c @@ -0,0 +1,148 @@ +/* + * Power Management device simulation in PKUnity SoC + * + * Copyright (C) 2010-2012 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. + */ +#include "hw.h" +#include "sysbus.h" + +#undef DEBUG_PUV3 +#include "puv3.h" + +typedef struct { + SysBusDevice busdev; + MemoryRegion iomem; + + uint32_t reg_PMCR; + uint32_t reg_PCGR; + uint32_t reg_PLL_SYS_CFG; + uint32_t reg_PLL_DDR_CFG; + uint32_t reg_PLL_VGA_CFG; + uint32_t reg_DIVCFG; +} puv3_pm_t; + +static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + puv3_pm_t *s = (puv3_pm_t *) opaque; + uint32_t ret; + + switch (offset) { + case 0x14: + ret = s->reg_PCGR; + break; + case 0x18: + ret = s->reg_PLL_SYS_CFG; + break; + case 0x1c: + ret = s->reg_PLL_DDR_CFG; + break; + case 0x20: + ret = s->reg_PLL_VGA_CFG; + break; + case 0x24: + ret = s->reg_DIVCFG; + break; + case 0x28: /* PLL SYS STATUS */ + ret = 0x00002401; + break; + case 0x2c: /* PLL DDR STATUS */ + ret = 0x00100c00; + break; + case 0x30: /* PLL VGA STATUS */ + ret = 0x00003801; + break; + case 0x34: /* DIV STATUS */ + ret = 0x22f52015; + break; + case 0x38: /* SW RESET */ + ret = 0x0; + break; + case 0x44: /* PLL DFC DONE */ + ret = 0x7; + break; + default: + hw_error("%s: Bad offset 0x%x\n", __func__, offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); + + return ret; +} + +static void puv3_pm_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) +{ + puv3_pm_t *s = (puv3_pm_t *) opaque; + + switch (offset) { + case 0x0: + s->reg_PMCR = value; + case 0x14: + s->reg_PCGR = value; + break; + case 0x18: + s->reg_PLL_SYS_CFG = value; + break; + case 0x1c: + s->reg_PLL_DDR_CFG = value; + break; + case 0x20: + s->reg_PLL_VGA_CFG = value; + break; + case 0x24: + case 0x38: + break; + default: + hw_error("%s: Bad offset 0x%x\n", __func__, offset); + } + DPRINTF("offset 0x%x, value 0x%x\n", offset, value); +} + +static const MemoryRegionOps puv3_pm_ops = { + .read = puv3_pm_read, + .write = puv3_pm_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static int puv3_pm_init(SysBusDevice *dev) +{ + puv3_pm_t *s = FROM_SYSBUS(puv3_pm_t, dev); + + s->reg_PCGR = 0x0; + + memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm", + PUV3_REGS_OFFSET); + sysbus_init_mmio(dev, &s->iomem); + + return 0; +} + +static void puv3_pm_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + + sdc->init = puv3_pm_init; +} + +static TypeInfo puv3_pm_info = { + .name = "puv3_pm", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(puv3_pm_t), + .class_init = puv3_pm_class_init, +}; + +static void puv3_pm_register_type(void) +{ + type_register_static(&puv3_pm_info); +} + +type_init(puv3_pm_register_type)