| Message ID | 3ad18bc590ef28e1526e8053568086b453e7ffde.1718211878.git.quic_mathbern@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | cpu: fix memleak of 'halt_cond' and 'thread' | expand |
On 12/6/24 19:04, Matheus Tavares Bernardino wrote: > Since a4c2735f35 (cpu: move Qemu[Thread|Cond] setup into common code, > 2024-05-30) these fields are now allocated at cpu_common_initfn(). So > let's make sure we also free them at cpu_common_finalize(). > > Furthermore, the code also frees these on round robin, but we missed > 'halt_cond'. > > Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> > --- > accel/tcg/tcg-accel-ops-rr.c | 1 + > hw/core/cpu-common.c | 3 +++ > 2 files changed, 4 insertions(+) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On 6/12/24 10:04, Matheus Tavares Bernardino wrote: > Since a4c2735f35 (cpu: move Qemu[Thread|Cond] setup into common code, > 2024-05-30) these fields are now allocated at cpu_common_initfn(). So > let's make sure we also free them at cpu_common_finalize(). > > Furthermore, the code also frees these on round robin, but we missed > 'halt_cond'. > > Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> > --- > accel/tcg/tcg-accel-ops-rr.c | 1 + > hw/core/cpu-common.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c > index 84c36c1450..48c38714bd 100644 > --- a/accel/tcg/tcg-accel-ops-rr.c > +++ b/accel/tcg/tcg-accel-ops-rr.c > @@ -329,6 +329,7 @@ void rr_start_vcpu_thread(CPUState *cpu) > /* we share the thread, dump spare data */ > g_free(cpu->thread); > qemu_cond_destroy(cpu->halt_cond); > + g_free(cpu->halt_cond); > cpu->thread = single_tcg_cpu_thread; > cpu->halt_cond = single_tcg_halt_cond; > > diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c > index bf1a7b8892..f131cde2c0 100644 > --- a/hw/core/cpu-common.c > +++ b/hw/core/cpu-common.c > @@ -286,6 +286,9 @@ static void cpu_common_finalize(Object *obj) > g_array_free(cpu->gdb_regs, TRUE); > qemu_lockcnt_destroy(&cpu->in_ioctl_lock); > qemu_mutex_destroy(&cpu->work_mutex); > + qemu_cond_destroy(cpu->halt_cond); > + g_free(cpu->halt_cond); > + g_free(cpu->thread); > } > > static int64_t cpu_common_get_arch_id(CPUState *cpu) Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
12.06.2024 20:04, Matheus Tavares Bernardino wrote: > Since a4c2735f35 (cpu: move Qemu[Thread|Cond] setup into common code, > 2024-05-30) these fields are now allocated at cpu_common_initfn(). So > let's make sure we also free them at cpu_common_finalize(). > > Furthermore, the code also frees these on round robin, but we missed > 'halt_cond'. Applied to trivial-patches, thanks! /mjt
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 84c36c1450..48c38714bd 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -329,6 +329,7 @@ void rr_start_vcpu_thread(CPUState *cpu) /* we share the thread, dump spare data */ g_free(cpu->thread); qemu_cond_destroy(cpu->halt_cond); + g_free(cpu->halt_cond); cpu->thread = single_tcg_cpu_thread; cpu->halt_cond = single_tcg_halt_cond; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index bf1a7b8892..f131cde2c0 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -286,6 +286,9 @@ static void cpu_common_finalize(Object *obj) g_array_free(cpu->gdb_regs, TRUE); qemu_lockcnt_destroy(&cpu->in_ioctl_lock); qemu_mutex_destroy(&cpu->work_mutex); + qemu_cond_destroy(cpu->halt_cond); + g_free(cpu->halt_cond); + g_free(cpu->thread); } static int64_t cpu_common_get_arch_id(CPUState *cpu)
Since a4c2735f35 (cpu: move Qemu[Thread|Cond] setup into common code, 2024-05-30) these fields are now allocated at cpu_common_initfn(). So let's make sure we also free them at cpu_common_finalize(). Furthermore, the code also frees these on round robin, but we missed 'halt_cond'. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> --- accel/tcg/tcg-accel-ops-rr.c | 1 + hw/core/cpu-common.c | 3 +++ 2 files changed, 4 insertions(+)