From patchwork Fri Mar 26 16:06:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Riku Voipio X-Patchwork-Id: 48699 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 263A8B7CF1 for ; Sat, 27 Mar 2010 05:57:36 +1100 (EST) Received: from localhost ([127.0.0.1]:33553 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NvDne-0006ja-5l for incoming@patchwork.ozlabs.org; Fri, 26 Mar 2010 13:58:26 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NvC5t-0004Ou-13 for qemu-devel@nongnu.org; Fri, 26 Mar 2010 12:09:09 -0400 Received: from [140.186.70.92] (port=41664 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NvC5j-0003f3-L2 for qemu-devel@nongnu.org; Fri, 26 Mar 2010 12:09:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NvC4G-0006wV-Kn for qemu-devel@nongnu.org; Fri, 26 Mar 2010 12:07:56 -0400 Received: from afflict.kos.to ([92.243.29.197]:33642) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NvC4C-0006ub-LG for qemu-devel@nongnu.org; Fri, 26 Mar 2010 12:07:25 -0400 Received: by afflict.kos.to (Postfix, from userid 1000) id A96FD26593; Fri, 26 Mar 2010 16:07:23 +0000 (UTC) From: Riku Voipio To: qemu-devel@nongnu.org Date: Fri, 26 Mar 2010 16:06:50 +0000 Message-Id: <39ff11f959d78f5a574831ecbf097db9e55aba5f.1269617186.git.riku.voipio@nokia.com> X-Mailer: git-send-email 1.6.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Riku Voipio Subject: [Qemu-devel] [PATCH 30/48] savevm and reset support for soc_dma X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Riku Voipio Signed-Off-By: Riku Voipio --- hw/soc_dma.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- hw/soc_dma.h | 4 ++- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/hw/soc_dma.c b/hw/soc_dma.c index 8147ed5..280fe92 100644 --- a/hw/soc_dma.c +++ b/hw/soc_dma.c @@ -20,6 +20,7 @@ #include "qemu-common.h" #include "qemu-timer.h" #include "soc_dma.h" +#include "hw.h" static void transfer_mem2mem(struct soc_dma_ch_s *ch) { @@ -228,12 +229,79 @@ void soc_dma_reset(struct soc_dma_s *soc) { struct dma_s *s = (struct dma_s *) soc; - s->soc.drqbmp = 0; + memset(s->soc.drqst, 0, sizeof(s->soc.drqst)); s->ch_enable_mask = 0; s->enabled_count = 0; soc_dma_ch_freq_update(s); } +static void soc_dma_save_state(QEMUFile *f, void *opaque) +{ + struct dma_s *s = (struct dma_s *)opaque; + int i; + + qemu_put_buffer(f, s->soc.drqst, sizeof(s->soc.drqst)); + qemu_put_sbe64(f, s->soc.freq); + qemu_put_be64(f, s->ch_enable_mask); + qemu_put_sbe64(f, s->channel_freq); + qemu_put_sbe32(f, s->enabled_count); + for (i = 0; i < s->chnum; i++) { + qemu_put_timer(f, s->ch[i].timer); + qemu_put_sbe32(f, s->ch[i].enable); + qemu_put_sbe32(f, s->ch[i].update); + qemu_put_sbe32(f, s->ch[i].bytes); + qemu_put_sbe32(f, s->ch[i].type[0]); + qemu_put_sbe32(f, s->ch[i].type[1]); +#if TARGET_PHYS_ADDR_BITS == 32 + qemu_put_be32(f, s->ch[i].vaddr[0]); + qemu_put_be32(f, s->ch[i].vaddr[1]); +#elif TARGET_PHYS_ADDR_BITS == 64 + qemu_put_be64(f, s->ch[i].vaddr[0]); + qemu_put_be64(f, s->ch[i].vaddr[1]); +#else +#error TARGET_PHYS_ADDR_BITS undefined +#endif + qemu_put_sbe32(f, s->ch[i].running); + } +} + +static int soc_dma_load_state(QEMUFile *f, void *opaque, int version_id) +{ + struct dma_s *s = (struct dma_s *)opaque; + int i; + + if (version_id) + return -EINVAL; + + qemu_get_buffer(f, s->soc.drqst, sizeof(s->soc.drqst)); + s->soc.freq = qemu_get_sbe64(f); + s->ch_enable_mask = qemu_get_be64(f); + s->channel_freq = qemu_get_sbe64(f); + s->enabled_count = qemu_get_sbe32(f); + for (i = 0; i < s->chnum; i++) { + qemu_get_timer(f, s->ch[i].timer); + s->ch[i].enable = qemu_get_sbe32(f); + s->ch[i].update = qemu_get_sbe32(f); + s->ch[i].bytes = qemu_get_sbe32(f); + s->ch[i].type[0] = qemu_get_sbe32(f); + s->ch[i].type[1] = qemu_get_sbe32(f); +#if TARGET_PHYS_ADDR_BITS == 32 + s->ch[i].vaddr[0] = qemu_get_be32(f); + s->ch[i].vaddr[1] = qemu_get_be32(f); +#elif TARGET_PHYS_ADDR_BITS == 64 + s->ch[i].vaddr[0] = qemu_get_be64(f); + s->ch[i].vaddr[1] = qemu_get_be64(f); +#else +#error TARGET_PHYS_ADDR_BITS undefined +#endif + s->ch[i].running = qemu_get_sbe32(f); + + soc_dma_ch_update(&s->ch[i]); + } + + return 0; +} + /* TODO: take a functional-clock argument */ struct soc_dma_s *soc_dma_init(int n) { @@ -251,6 +319,8 @@ struct soc_dma_s *soc_dma_init(int n) soc_dma_reset(&s->soc); fifo_size = 0; + register_savevm("soc_dma", -1, 0, + soc_dma_save_state, soc_dma_load_state, s); return &s->soc; } diff --git a/hw/soc_dma.h b/hw/soc_dma.h index c0ebb8d..6bfd3a8 100644 --- a/hw/soc_dma.h +++ b/hw/soc_dma.h @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define DMA_MAX_DRQ 96 + struct soc_dma_s; struct soc_dma_ch_s; typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len); @@ -65,7 +67,7 @@ struct soc_dma_ch_s { struct soc_dma_s { /* Following fields are set by the SoC DMA module and can be used * by anybody. */ - uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ + uint8_t drqst[DMA_MAX_DRQ]; /* Is zeroed by soc_dma_reset() */ qemu_irq *drq; void *opaque; int64_t freq;