From patchwork Thu Oct 27 12:10:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcelo Tosatti X-Patchwork-Id: 122133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 93C1F1007D8 for ; Thu, 27 Oct 2011 23:13:16 +1100 (EST) Received: from localhost ([::1]:46208 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJOpZ-0001zU-IE for incoming@patchwork.ozlabs.org; Thu, 27 Oct 2011 08:13:09 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJOoI-0006dv-Bf for qemu-devel@nongnu.org; Thu, 27 Oct 2011 08:11:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJOoH-0005EF-4Q for qemu-devel@nongnu.org; Thu, 27 Oct 2011 08:11:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:56095) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJOoG-0005Dp-SU for qemu-devel@nongnu.org; Thu, 27 Oct 2011 08:11:49 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9RCBld6020322 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 27 Oct 2011 08:11:47 -0400 Received: from ns3.rdu.redhat.com (ns3.rdu.redhat.com [10.11.255.199]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p9RCBlmw000534; Thu, 27 Oct 2011 08:11:47 -0400 Received: from amt.cnet (vpn-9-128.rdu.redhat.com [10.11.9.128]) by ns3.rdu.redhat.com (8.13.8/8.13.8) with ESMTP id p9RCBkdV022261; Thu, 27 Oct 2011 08:11:46 -0400 Received: from amt.cnet (amt.cnet [127.0.0.1]) by amt.cnet (Postfix) with ESMTP id B23AC6520FD; Thu, 27 Oct 2011 10:10:31 -0200 (BRST) Received: (from marcelo@localhost) by amt.cnet (8.14.5/8.14.5/Submit) id p9RCAUQq029976; Thu, 27 Oct 2011 10:10:30 -0200 From: Marcelo Tosatti To: Anthony Liguori Date: Thu, 27 Oct 2011 10:10:17 -0200 Message-Id: <38d2c27ea68468bd2fdaa19c74d9e6d290f94777.1319717419.git.mtosatti@redhat.com> In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 209.132.183.28 Cc: Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [Qemu-devel] [PATCH 4/6] Revert "kvm: support TSC deadline MSR" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3. New patch with subsections will follow. Signed-off-by: Marcelo Tosatti --- target-i386/cpu.h | 4 +--- target-i386/kvm.c | 14 -------------- target-i386/machine.c | 1 - 3 files changed, 1 insertions(+), 18 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index a973f2e..ae36489 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,7 +283,6 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) -#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -688,7 +687,6 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; - uint64_t tsc_deadline; uint64_t mcg_status; @@ -949,7 +947,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list_id x86_cpu_list #define cpudef_setup x86_cpudef_setup -#define CPU_SAVE_VERSION 13 +#define CPU_SAVE_VERSION 12 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 90a6ffb..b6eef04 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -59,7 +59,6 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; -static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; static int lm_capable_kernel; @@ -569,10 +568,6 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hsave_pa = true; continue; } - if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { - has_msr_tsc_deadline = true; - continue; - } } } @@ -886,9 +881,6 @@ static int kvm_put_msrs(CPUState *env, int level) if (has_msr_hsave_pa) { kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); } - if (has_msr_tsc_deadline) { - kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); - } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1135,9 +1127,6 @@ static int kvm_get_msrs(CPUState *env) if (has_msr_hsave_pa) { msrs[n++].index = MSR_VM_HSAVE_PA; } - if (has_msr_tsc_deadline) { - msrs[n++].index = MSR_IA32_TSCDEADLINE; - } if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1206,9 +1195,6 @@ static int kvm_get_msrs(CPUState *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; - case MSR_IA32_TSCDEADLINE: - env->tsc_deadline = msrs[i].data; - break; case MSR_VM_HSAVE_PA: env->vm_hsave = msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index 25fa97d..9aca8e0 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -410,7 +410,6 @@ static const VMStateDescription vmstate_cpu = { VMSTATE_UINT64_V(xcr0, CPUState, 12), VMSTATE_UINT64_V(xstate_bv, CPUState, 12), VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12), - VMSTATE_UINT64_V(tsc_deadline, CPUState, 13), VMSTATE_END_OF_LIST() /* The above list is not sorted /wrt version numbers, watch out! */ },