From patchwork Tue Feb 16 22:21:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 45569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A4EACB7C09 for ; Wed, 17 Feb 2010 10:46:10 +1100 (EST) Received: from localhost ([127.0.0.1]:38994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhWpb-0003QH-Kn for incoming@patchwork.ozlabs.org; Tue, 16 Feb 2010 18:27:51 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NhWgm-0000qJ-Lc for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:44 -0500 Received: from [199.232.76.173] (port=53097 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhWgm-0000ps-3I for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:44 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NhWgh-0006or-6s for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:43 -0500 Received: from are.twiddle.net ([75.149.56.221]:37893) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NhWgg-0006oc-3g for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:38 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 50263EF6; Tue, 16 Feb 2010 15:18:33 -0800 (PST) Message-Id: <37a1bc1f84ee91f9270f26f4ad860e93fc7e1ceb.1266362140.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Tue, 16 Feb 2010 14:21:19 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 5/6] tcg-sparc: Implement ANDC. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 6 ++++++ tcg/sparc/tcg-target.h | 2 ++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index b876b3a..c1761cc 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -220,6 +220,7 @@ static inline int tcg_target_const_match(tcg_target_long val, #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) +#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) @@ -1108,6 +1109,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, OP_32_64(and): c = ARITH_AND; goto gen_arith; + OP_32_64(andc): + c = ARITH_ANDN; + goto gen_arith; OP_32_64(or): c = ARITH_OR; goto gen_arith; @@ -1313,6 +1317,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_remu_i32, { "r", "r", "rJ" } }, { INDEX_op_sub_i32, { "r", "r", "rJ" } }, { INDEX_op_and_i32, { "r", "r", "rJ" } }, + { INDEX_op_andc_i32, { "r", "r", "rJ" } }, { INDEX_op_or_i32, { "r", "r", "rJ" } }, { INDEX_op_xor_i32, { "r", "r", "rJ" } }, @@ -1367,6 +1372,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_remu_i64, { "r", "r", "rJ" } }, { INDEX_op_sub_i64, { "r", "r", "rJ" } }, { INDEX_op_and_i64, { "r", "r", "rJ" } }, + { INDEX_op_andc_i64, { "r", "r", "rJ" } }, { INDEX_op_or_i64, { "r", "r", "rJ" } }, { INDEX_op_xor_i64, { "r", "r", "rJ" } }, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index f5ee205..4ea0c19 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -93,12 +93,14 @@ enum { #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_not_i32 +#define TCG_TARGET_HAS_andc_i32 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_ext32s_i64 #define TCG_TARGET_HAS_ext32u_i64 #define TCG_TARGET_HAS_neg_i64 #define TCG_TARGET_HAS_not_i64 +#define TCG_TARGET_HAS_andc_i64 #endif //#define TCG_TARGET_HAS_bswap32_i32