From patchwork Mon Mar 19 22:57:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 147705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D705CB6EE6 for ; Tue, 20 Mar 2012 11:33:02 +1100 (EST) Received: from localhost ([::1]:36454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lYG-0005Cp-EX for incoming@patchwork.ozlabs.org; Mon, 19 Mar 2012 18:59:44 -0400 Received: from eggs.gnu.org ([208.118.235.92]:55682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lXB-0002mR-Qx for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S9lX5-000108-Dz for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:31109) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S9lX5-0000zj-3T for qemu-devel@nongnu.org; Mon, 19 Mar 2012 18:58:31 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q2JMwThH022761 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 19 Mar 2012 18:58:29 -0400 Received: from trasno.mitica (ovpn-116-17.ams2.redhat.com [10.36.116.17]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q2JMw4oZ017718; Mon, 19 Mar 2012 18:58:28 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2012 23:57:47 +0100 Message-Id: <34b96a61bc66cce4d83c638326fd4e537622878b.1332197811.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 19/36] mips: make mvp an embedded struct instead of a pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adjust all callers. Signed-off-by: Juan Quintela --- hw/mips_malta.c | 4 ++-- target-mips/cpu.h | 4 ++-- target-mips/machine.c | 12 ++++++------ target-mips/op_helper.c | 30 +++++++++++++++++------------- target-mips/translate.c | 6 +++--- target-mips/translate_init.c | 14 ++++++-------- 6 files changed, 36 insertions(+), 34 deletions(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 4752bb2..a1cdab5 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -745,8 +745,8 @@ static int64_t load_kernel (void) static void malta_mips_config(CPUMIPSState *env) { - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | - ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC); + env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | + ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC); } static void main_cpu_reset(void *opaque) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7430aa5..9450f0c 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -473,7 +473,7 @@ struct CPUMIPSState { CPU_COMMON - CPUMIPSMVPContext *mvp; + CPUMIPSMVPContext mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; #endif @@ -675,7 +675,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) int active = 1; /* Check that the VPE is enabled. */ - if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { + if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) { active = 0; } /* Check that the VPE is activated. */ diff --git a/target-mips/machine.c b/target-mips/machine.c index 23504ba..d5d8865 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque) save_fpu(f, &env->active_fpu); /* Save MVP */ - qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); - qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); - qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); + qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl); + qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0); + qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1); /* Save TLB */ qemu_put_be32s(f, &env->tlb->nb_tlb); @@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) load_fpu(f, &env->active_fpu); /* Load MVP */ - qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); - qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); - qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); + qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl); + qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0); + qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1); /* Load TLB */ qemu_get_be32s(f, &env->tlb->nb_tlb); diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 3a20731..860b275 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -909,17 +909,17 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) /* CP0 helpers */ target_ulong helper_mfc0_mvpcontrol (void) { - return env->mvp->CP0_MVPControl; + return env->mvp.CP0_MVPControl; } target_ulong helper_mfc0_mvpconf0 (void) { - return env->mvp->CP0_MVPConf0; + return env->mvp.CP0_MVPConf0; } target_ulong helper_mfc0_mvpconf1 (void) { - return env->mvp->CP0_MVPConf1; + return env->mvp.CP0_MVPConf1; } target_ulong helper_mfc0_random (void) @@ -1172,13 +1172,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1) if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | (1 << CP0MVPCo_EVP); - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0MVPCo_STLB); - newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); + } + newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask); // TODO: Enable/disable shared TLB, enable/disable VPEs. - env->mvp->CP0_MVPControl = newval; + env->mvp.CP0_MVPControl = newval; } void helper_mtc0_vpecontrol (target_ulong arg1) @@ -1266,9 +1267,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1) uint32_t mask = 0; uint32_t newval; - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | (0xff << CP0VPEC1_NCP1); + } newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); /* UDI not implemented. */ @@ -1325,8 +1327,9 @@ void helper_mtc0_tcbind (target_ulong arg1) uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0TCBd_CurVPE); + } newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); env->active_tc.CP0_TCBind = newval; } @@ -1338,8 +1341,9 @@ void helper_mttc0_tcbind (target_ulong arg1) uint32_t newval; CPUMIPSState *other = mips_cpu_map_tc(&other_tc); - if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0TCBd_CurVPE); + } if (other_tc == other->current_tc) { newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); other->active_tc.CP0_TCBind = newval; @@ -1910,12 +1914,12 @@ target_ulong helper_emt(void) target_ulong helper_dvpe(void) { CPUMIPSState *other_cpu = first_cpu; - target_ulong prev = env->mvp->CP0_MVPControl; + target_ulong prev = env->mvp.CP0_MVPControl; do { /* Turn off all VPEs except the one executing the dvpe. */ if (other_cpu != env) { - other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); + other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } other_cpu = other_cpu->next_cpu; @@ -1926,14 +1930,14 @@ target_ulong helper_dvpe(void) target_ulong helper_evpe(void) { CPUMIPSState *other_cpu = first_cpu; - target_ulong prev = env->mvp->CP0_MVPControl; + target_ulong prev = env->mvp.CP0_MVPControl; do { if (other_cpu != env /* If the VPE is WFI, don't disturb its sleep. */ && !mips_vpe_is_wfi(other_cpu)) { /* Enable the VPE. */ - other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP); mips_vpe_wake(other_cpu); /* And wake it up. */ } other_cpu = other_cpu->next_cpu; diff --git a/target-mips/translate.c b/target-mips/translate.c index a663b74..6afa923 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5526,7 +5526,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) tcg_gen_movi_tl(t0, -1); else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > - (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) tcg_gen_movi_tl(t0, -1); else if (u == 0) { switch (rt) { @@ -5744,7 +5744,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) /* NOP */ ; else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > - (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) /* NOP */ ; else if (u == 0) { switch (rd) { @@ -12820,7 +12820,7 @@ void cpu_state_reset(CPUMIPSState *env) if (!env->cpu_index) { /* VPE0 starts up enabled. */ - env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP); env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); /* TC0 starts up unhalted. */ diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c39138f..54fd1eb 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) static void mvp_init (CPUMIPSState *env, const mips_def_t *def) { - env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); - /* MVPConf1 implemented, TLB sharable, no gating storage support, programmable cache partitioning implemented, number of allocatable and sharable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ - env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | - (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | + env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | // TODO: actually do 2 VPEs. // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | // (0x04 << CP0MVPC0_PTC); - (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | - (0x00 << CP0MVPC0_PTC); + (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | + (0x00 << CP0MVPC0_PTC); #if !defined(CONFIG_USER_ONLY) /* Usermode has no TLB support */ - env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); + env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); #endif /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ - env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x1 << CP0MVPC1_PCP1); }