@@ -745,8 +745,8 @@ static int64_t load_kernel (void)
static void malta_mips_config(CPUMIPSState *env)
{
- env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
- ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
+ env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
+ ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
}
static void main_cpu_reset(void *opaque)
@@ -473,7 +473,7 @@ struct CPUMIPSState {
CPU_COMMON
- CPUMIPSMVPContext *mvp;
+ CPUMIPSMVPContext mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
#endif
@@ -675,7 +675,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
int active = 1;
/* Check that the VPE is enabled. */
- if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+ if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
active = 0;
}
/* Check that the VPE is activated. */
@@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque)
save_fpu(f, &env->active_fpu);
/* Save MVP */
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Save TLB */
qemu_put_be32s(f, &env->tlb->nb_tlb);
@@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
load_fpu(f, &env->active_fpu);
/* Load MVP */
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Load TLB */
qemu_get_be32s(f, &env->tlb->nb_tlb);
@@ -909,17 +909,17 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
/* CP0 helpers */
target_ulong helper_mfc0_mvpcontrol (void)
{
- return env->mvp->CP0_MVPControl;
+ return env->mvp.CP0_MVPControl;
}
target_ulong helper_mfc0_mvpconf0 (void)
{
- return env->mvp->CP0_MVPConf0;
+ return env->mvp.CP0_MVPConf0;
}
target_ulong helper_mfc0_mvpconf1 (void)
{
- return env->mvp->CP0_MVPConf1;
+ return env->mvp.CP0_MVPConf1;
}
target_ulong helper_mfc0_random (void)
@@ -1172,13 +1172,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
(1 << CP0MVPCo_EVP);
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0MVPCo_STLB);
- newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
+ }
+ newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask);
// TODO: Enable/disable shared TLB, enable/disable VPEs.
- env->mvp->CP0_MVPControl = newval;
+ env->mvp.CP0_MVPControl = newval;
}
void helper_mtc0_vpecontrol (target_ulong arg1)
@@ -1266,9 +1267,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
uint32_t mask = 0;
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
(0xff << CP0VPEC1_NCP1);
+ }
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
/* UDI not implemented. */
@@ -1325,8 +1327,9 @@ void helper_mtc0_tcbind (target_ulong arg1)
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
env->active_tc.CP0_TCBind = newval;
}
@@ -1338,8 +1341,9 @@ void helper_mttc0_tcbind (target_ulong arg1)
uint32_t newval;
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
- if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
if (other_tc == other->current_tc) {
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
other->active_tc.CP0_TCBind = newval;
@@ -1910,12 +1914,12 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(void)
{
CPUMIPSState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
/* Turn off all VPEs except the one executing the dvpe. */
if (other_cpu != env) {
- other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
other_cpu = other_cpu->next_cpu;
@@ -1926,14 +1930,14 @@ target_ulong helper_dvpe(void)
target_ulong helper_evpe(void)
{
CPUMIPSState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
if (other_cpu != env
/* If the VPE is WFI, don't disturb its sleep. */
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
- other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu); /* And wake it up. */
}
other_cpu = other_cpu->next_cpu;
@@ -5526,7 +5526,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
tcg_gen_movi_tl(t0, -1);
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
tcg_gen_movi_tl(t0, -1);
else if (u == 0) {
switch (rt) {
@@ -5744,7 +5744,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
/* NOP */ ;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
/* NOP */ ;
else if (u == 0) {
switch (rd) {
@@ -12820,7 +12820,7 @@ void cpu_state_reset(CPUMIPSState *env)
if (!env->cpu_index) {
/* VPE0 starts up enabled. */
- env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
/* TC0 starts up unhalted. */
@@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
- env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
- (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+ env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+ (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
// TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
// (0x04 << CP0MVPC0_PTC);
- (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
- (0x00 << CP0MVPC0_PTC);
+ (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+ (0x00 << CP0MVPC0_PTC);
#if !defined(CONFIG_USER_ONLY)
/* Usermode has no TLB support */
- env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+ env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
#endif
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
- env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+ env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
Adjust all callers. Signed-off-by: Juan Quintela <quintela@redhat.com> --- hw/mips_malta.c | 4 ++-- target-mips/cpu.h | 4 ++-- target-mips/machine.c | 12 ++++++------ target-mips/op_helper.c | 30 +++++++++++++++++------------- target-mips/translate.c | 6 +++--- target-mips/translate_init.c | 14 ++++++-------- 6 files changed, 36 insertions(+), 34 deletions(-)