From patchwork Thu Jun 26 05:02:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 364238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 57BE01400AB for ; Thu, 26 Jun 2014 15:03:08 +1000 (EST) Received: from localhost ([::1]:42253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01py-0001O9-BF for incoming@patchwork.ozlabs.org; Thu, 26 Jun 2014 01:03:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pN-0000HA-Lg for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X01pH-0006jA-MR for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:29 -0400 Received: from mail-ig0-x22d.google.com ([2607:f8b0:4001:c05::22d]:36708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pH-0006iZ-8B for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:23 -0400 Received: by mail-ig0-f173.google.com with SMTP id uq10so292554igb.6 for ; Wed, 25 Jun 2014 22:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=yJyAQyj+sGT27g5JU+Vzn90mMy4R10mJBtcNVz4NUHk=; b=hc499R8HWz6VtcpF/CzTdrBMGfPBTCSumwDfaVuou/3BdgjnyBU5NW1n0q/bFi1D/v eXBWlNAOBbpye/EcbnecLDuKmGyF/6qGziW9el63hRzBY3nn5S7blsO5NoeTLxtkVs0m Al/qxrRXQFCXxmBpnxvrDLvR/rfIu3w5Do3H3zCYsnvx2wTL7hMsoh9ajJs+JEDErT6I +nNJMKYx2qBHnioR05kCzwCWbd47JNKKsZCHbJr5YGFf/33Cllnl9YtvZI42tsvlX77N WRGURWmi0Y6clBxCI8R3811AdVpJ5p1oJte2vPU6bteXrkbHUJ4aXk/avqFDR/GXHeCm NROA== X-Received: by 10.50.2.71 with SMTP id 7mr1397967igs.32.1403758942663; Wed, 25 Jun 2014 22:02:22 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id qa4sm1075003igb.10.2014.06.25.22.02.19 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 25 Jun 2014 22:02:22 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Thu, 26 Jun 2014 15:02:16 +1000 Message-Id: <31da3bcf3ec2da847199113f16bd402e2707b927.1403757527.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c05::22d Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, cov@codeaurora.org, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v2 3/7] target-arm: Add arm_ccnt_enabled function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Include a helper function to determine if the CCNT counter is enabled as well as the constants used to mask the pmccfiltr_el0 and c9_pmxevtyper registers. Signed-off-by: Alistair Francis --- target-arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ce986ee..141e252 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -547,6 +547,46 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) } #ifndef CONFIG_USER_ONLY +#define PMCCFILTR_NSH 0x8000000 +#define PMCCFILTR_P 0x80000000 +#define PMCCFILTR_U 0x40000000 + +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 + +static bool arm_ccnt_enabled(CPUARMState *env) +{ + /* This does not support checking for the secure/non-secure + * components of the PMCCFILTR_EL0 register + */ + + if (!(env->cp15.c9_pmcr & PMCRE)) { + return 0; + } + + if (arm_current_pl(env) == 2) { + if (!(env->cp15.pmccfiltr_el0 & PMCCFILTR_NSH)) { + return 0; + } + } else if (arm_current_pl(env) == 1) { + if (env->cp15.pmccfiltr_el0 & PMCCFILTR_P) { + return 0; + } else if (env->cp15.c9_pmxevtyper & PMXEVTYPER_P) { + return 0; + } + } else if (arm_current_pl(env) == 0) { + if (env->cp15.pmccfiltr_el0 & PMCCFILTR_U) { + return 0; + } else if (env->cp15.c9_pmxevtyper & PMXEVTYPER_U) { + return 0; + } + } + + return 1; +} +#endif + +#ifndef CONFIG_USER_ONLY static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {