From patchwork Tue Feb 9 22:14:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 581092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0AA48140BA2 for ; Wed, 10 Feb 2016 09:20:13 +1100 (AEDT) Received: from localhost ([::1]:32948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTGdm-00086i-RZ for incoming@patchwork.ozlabs.org; Tue, 09 Feb 2016 17:20:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46669) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTGb7-0003Xm-GU for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTGb2-0000v3-Kt for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:25 -0500 Received: from mail-bl2nam02on0055.outbound.protection.outlook.com ([104.47.38.55]:47396 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTGb2-0000uB-Ec for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:20 -0500 Received: from SN1NAM02FT026.eop-nam02.prod.protection.outlook.com (10.152.72.51) by SN1NAM02HT245.eop-nam02.prod.protection.outlook.com (10.152.72.215) with Microsoft SMTP Server (TLS) id 15.1.409.7; Tue, 9 Feb 2016 22:17:18 +0000 Authentication-Results: spf=fail (sender IP is 149.199.60.96) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none; linaro.org; dmarc=none action=none header.from=xilinx.com; Received-SPF: Fail (protection.outlook.com: domain of xilinx.com does not designate 149.199.60.96 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.96; helo=xsj-tvapsmtpgw01; Received: from xsj-tvapsmtpgw01 (149.199.60.96) by SN1NAM02FT026.mail.protection.outlook.com (10.152.72.97) with Microsoft SMTP Server (TLS) id 15.1.409.7 via Frontend Transport; Tue, 9 Feb 2016 22:17:18 +0000 Received: from 172-16-1-203.xilinx.com ([172.16.1.203]:35334 helo=xsj-tvapsmtp02.xilinx.com) by xsj-tvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1aTGaz-0002mO-Bs; Tue, 09 Feb 2016 14:17:17 -0800 Received: from [127.0.0.1] (port=42553 helo=tsj-smtp-dlp1.xlnx.xilinx.com) by xsj-tvapsmtp02.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1aTGaz-0007Zw-61; Tue, 09 Feb 2016 14:17:17 -0800 Received: from xsj-tvapsmtp02 (xsj-tvapsmtp02.xilinx.com [172.16.1.203]) by tsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u19MBaft011521; Tue, 9 Feb 2016 14:11:36 -0800 Received: from [172.19.74.182] (port=49714 helo=xsjalistai50.xlnx.xilinx.com) by xsj-tvapsmtp02 with esmtp (Exim 4.63) (envelope-from ) id 1aTGay-0007Zt-Cl; Tue, 09 Feb 2016 14:17:16 -0800 From: Alistair Francis To: , Date: Tue, 9 Feb 2016 14:14:41 -0800 Message-ID: <30297902aab7203c57444d3f6a3c0da6aee3ce97.1455055858.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22054.006 X-TM-AS-Result: No--18.479-7.0-31-10 X-imss-scan-details: No--18.479-7.0-31-10 X-TMASE-MatchedRID: HViwKOuvIQo3AywPeXaPsy2taMI32X8W0nXvwjW2mSXJYIv7y0tu9lUn QAOplXiG0TB48RcQxBCcAs5VJqoVZWKztShDQzFuqeBupNgLgYf54F/2i/DwjVmmz7LVVfOpoud 5cX9BENNRUSirfNnIk1vrM+4RbbUVKmzIo+yV5o9CnGIuUMP0VZIP/SO+XIBSEvoxTu3fj1ug/2 Cq6PCYoWxsZjteC2njjf93Q249wjXpzoZfJABOugPRhGX0wT3l7T7u8yAbuqNm+6Fpy57LxXm8t 2ifVKz3WGfm6ffYK9DHG+BsUZTTom8LdPkpremHFxqdoICq+IZU3K6aV1ad7efL+zKjW08PJRy0 pjer4Ox9ZOud1SV64OdTsIISNsrfFkrTnESQKQJDXrKt1VG3HH3/PYNiodjtxKLCLOyCW5BDG3W PfH3HeC6P0DpTtHwiyCcUxGomiTV5OFLKjahJ2cg6fo0rxLVrh+w9Wz/xXDrxxaAXDrCns4pGtC muhU7rXui6/+tK/z9o/Q6UoVJMJow2gDOr2cehYwaJXrf2IXQ4WsSNiH/UXm7gWSfKrKyEpRrMk aeNIWNdP9WMhYexLJRwruMBkkJCGnt8LtZARPf0hv/rD7WVZIEcpMn6x9cZN4xXtLcoxj2f6BCW qCgLSy0Z2IlORVSLgAYZl0IbohgfE8yM4pjsDwtuKBGekqUpPjKoPgsq7cA= X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.96; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(6806005)(5001770100001)(86362001)(33646002)(85426001)(2950100001)(87936001)(229853001)(118296001)(77096005)(48376002)(105606002)(106466001)(5003940100001)(50226001)(5003600100002)(64026002)(5001960100002)(36756003)(47776003)(50986999)(76176999)(92566002)(5008740100001)(189998001)(2906002)(4326007)(1220700001)(1096002)(586003)(50466002)(19580405001)(19580395003)(11100500001)(107986001); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1NAM02HT245; H:xsj-tvapsmtpgw01; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: c76533a3-0ed0-449d-2c82-08d3319ec5e6 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT245; X-Microsoft-Antispam-PRVS: <90cab1fde7784763b5c8e8a23065cb06@SN1NAM02HT245.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(13024025)(8121501046)(13015025)(13017025)(13018025)(5005006)(13023025)(3002001)(10201501046); SRVR:SN1NAM02HT245; BCL:0; PCL:0; RULEID:; SRVR:SN1NAM02HT245; X-Forefront-PRVS: 08476BC6EF X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2016 22:17:18.0255 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT245 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.38.55 Cc: edgar.iglesias@xilinx.com, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, alex.bennee@linaro.org, afaerber@suse.de, fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v4 02/16] register: Add Register API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This API provides some encapsulation of registers and factors our some common functionality to common code. Bits of device state (usually MMIO registers), often have all sorts of access restrictions and semantics associated with them. This API allow you to define what those restrictions are on a bit-by-bit basis. Helper functions are then used to access the register which observe the semantics defined by the RegisterAccessInfo struct. Some features: Bits can be marked as read_only (ro field) Bits can be marked as write-1-clear (w1c field) Bits can be marked as reserved (rsvd field) Reset values can be defined (reset) Bits can throw guest errors when written certain values (ge0, ge1) Bits can throw unimp errors when written certain values (ui0, ui1) Bits can be marked clear on read (cor) Pre and post action callbacks can be added to read and write ops Verbose debugging info can be enabled/disabled Useful for defining device register spaces in a data driven way. Cuts down on a lot of the verbosity and repetition in the switch-case blocks in the standard foo_mmio_read/write functions. Also useful for automated generation of device models from hardware design sources. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis --- V4: - Rebase - Remove the guest error masking - Simplify the unimplemented masking - Use the reserved value in the write calculations - Remove read_lite and write_lite - General fixes to asserts and log printing V3: - Address some comments from Fred hw/core/Makefile.objs | 1 + hw/core/register.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/register.h | 111 ++++++++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 hw/core/register.c create mode 100644 include/hw/register.h diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index abb3560..bf95db5 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -14,4 +14,5 @@ common-obj-$(CONFIG_SOFTMMU) += machine.o common-obj-$(CONFIG_SOFTMMU) += null-machine.o common-obj-$(CONFIG_SOFTMMU) += loader.o common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o +common-obj-$(CONFIG_SOFTMMU) += register.o common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o diff --git a/hw/core/register.c b/hw/core/register.c new file mode 100644 index 0000000..7e47df5 --- /dev/null +++ b/hw/core/register.c @@ -0,0 +1,152 @@ +/* + * Register Definition API + * + * Copyright (c) 2013 Xilinx Inc. + * Copyright (c) 2013 Peter Crosthwaite + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "hw/register.h" +#include "hw/qdev.h" +#include "qemu/log.h" + +static inline void register_write_log(int mask, RegisterInfo *reg, int dir, + uint64_t val, const char *msg, + const char *reason) +{ + qemu_log_mask(mask, "%s:%s bits %#" PRIx64 " %s write of %d%s%s\n", + reg->prefix, reg->access->name, val, msg, dir, + reason ? ": " : "", reason ? reason : ""); +} + +static inline void register_write_val(RegisterInfo *reg, uint64_t val) +{ + g_assert(reg->data); + + switch (reg->data_size) { + case 1: + *(uint8_t *)reg->data = val; + break; + case 2: + *(uint16_t *)reg->data = val; + break; + case 4: + *(uint32_t *)reg->data = val; + break; + case 8: + *(uint64_t *)reg->data = val; + break; + default: + g_assert_not_reached(); + } +} + +static inline uint64_t register_read_val(RegisterInfo *reg) +{ + switch (reg->data_size) { + case 1: + return *(uint8_t *)reg->data; + case 2: + return *(uint16_t *)reg->data; + case 4: + return *(uint32_t *)reg->data; + case 8: + return *(uint64_t *)reg->data; + default: + g_assert_not_reached(); + } + return 0; /* unreachable */ +} + +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we) +{ + uint64_t old_val, new_val, test, no_w_mask; + const RegisterAccessInfo *ac; + + assert(reg); + + ac = reg->access; + + if (!ac || !ac->name) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state " + "(written value: %#" PRIx64 ")\n", reg->prefix, val); + return; + } + + old_val = reg->data ? register_read_val(reg) : ac->reset; + + test = (old_val ^ val) & ac->rsvd; + if (test) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit" + "fields: %#" PRIx64 ")\n", reg->prefix, test); + } + + test = val & ac->unimp; + if (test) { + qemu_log_mask(LOG_UNIMP, + "%s:%s writing %#" PRIx64 " to unimplemented bits:" \ + " %#" PRIx64 "", + reg->prefix, reg->access->name, val, ac->unimp); + } + + + no_w_mask = ac->ro | ac->w1c | ac->rsvd | ~we; + new_val = (val & ~no_w_mask) | (old_val & no_w_mask); + new_val &= ~(val & ac->w1c); + + if (ac->pre_write) { + new_val = ac->pre_write(reg, new_val); + } + + if (reg->debug) { + qemu_log("%s:%s: write of value %#" PRIx64 "\n", reg->prefix, ac->name, + new_val); + } + + register_write_val(reg, new_val); + + if (ac->post_write) { + ac->post_write(reg, new_val); + } +} + +uint64_t register_read(RegisterInfo *reg) +{ + uint64_t ret; + const RegisterAccessInfo *ac; + + assert(reg); + + ac = reg->access; + if (!ac || !ac->name) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device state\n", + reg->prefix); + return 0; + } + + ret = reg->data ? register_read_val(reg) : ac->reset; + + register_write_val(reg, ret & ~ac->cor); + + if (ac->post_read) { + ret = ac->post_read(reg, ret); + } + + if (reg->debug) { + qemu_log("%s:%s: read of value %#" PRIx64 "\n", reg->prefix, + ac->name, ret); + } + + return ret; +} + +void register_reset(RegisterInfo *reg) +{ + g_assert(reg); + g_assert(reg->data); + g_assert(reg->access); + + register_write_val(reg, reg->access->reset); +} diff --git a/include/hw/register.h b/include/hw/register.h new file mode 100644 index 0000000..444239c --- /dev/null +++ b/include/hw/register.h @@ -0,0 +1,111 @@ +/* + * Register Definition API + * + * Copyright (c) 2013 Xilinx Inc. + * Copyright (c) 2013 Peter Crosthwaite + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#ifndef REGISTER_H +#define REGISTER_H + +#include "exec/memory.h" + +typedef struct RegisterInfo RegisterInfo; +typedef struct RegisterAccessInfo RegisterAccessInfo; + +/** + * Access description for a register that is part of guest accessible device + * state. + * + * @name: String name of the register + * @ro: whether or not the bit is read-only + * @w1c: bits with the common write 1 to clear semantic. + * @reset: reset value. + * @cor: Bits that are clear on read + * @rsvd: Bits that are reserved and should not be changed + * + * @ui1: Bits that when written 1 indicate use of an unimplemented feature + * @ui0: Bits that when written 0 indicate use of an unimplemented feature + * + * @pre_write: Pre write callback. Passed the value that's to be written, + * immediately before the actual write. The returned value is what is written, + * giving the handler a chance to modify the written value. + * @post_write: Post write callback. Passed the written value. Most write side + * effects should be implemented here. + * + * @post_read: Post read callback. Passes the value that is about to be returned + * for a read. The return value from this function is what is ultimately read, + * allowing this function to modify the value before return to the client. + */ + +struct RegisterAccessInfo { + const char *name; + uint64_t ro; + uint64_t w1c; + uint64_t reset; + uint64_t cor; + uint64_t rsvd; + uint64_t unimp; + + uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val); + void (*post_write)(RegisterInfo *reg, uint64_t val); + + uint64_t (*post_read)(RegisterInfo *reg, uint64_t val); +}; + +/** + * A register that is part of guest accessible state + * @data: pointer to the register data. Will be cast + * to the relevant uint type depending on data_size. + * @data_size: Size of the register in bytes. Must be + * 1, 2, 4 or 8 + * + * @access: Access description of this register + * + * @debug: Whether or not verbose debug is enabled + * @prefix: String prefix for log and debug messages + * + * @opaque: Opaque data for the register + */ + +struct RegisterInfo { + /* */ + void *data; + int data_size; + + const RegisterAccessInfo *access; + + bool debug; + const char *prefix; + + void *opaque; +}; + +/** + * write a value to a register, subject to its restrictions + * @reg: register to write to + * @val: value to write + * @we: write enable mask + */ + +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we); + +/** + * read a value from a register, subject to its restrictions + * @reg: register to read from + * returns: value read + */ + +uint64_t register_read(RegisterInfo *reg); + +/** + * reset a register + * @reg: register to reset + */ + +void register_reset(RegisterInfo *reg); + +#endif