From patchwork Wed Jun 26 09:13:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 254636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 77DC72C037B for ; Wed, 26 Jun 2013 19:17:25 +1000 (EST) Received: from localhost ([::1]:37662 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Urlqt-0008OB-8N for incoming@patchwork.ozlabs.org; Wed, 26 Jun 2013 05:17:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43484) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrloN-0004xu-62 for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UrloL-0002ZI-09 for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:47 -0400 Received: from [222.73.24.84] (port=12697 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrloK-0002Y0-L4 for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:44 -0400 X-IronPort-AV: E=Sophos;i="4.87,943,1363104000"; d="scan'208";a="7688751" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 26 Jun 2013 17:11:36 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r5Q9EUvI020395; Wed, 26 Jun 2013 17:14:32 +0800 Received: from G08FNSTD100614.fnst.cn.fujitsu.com ([10.167.233.156]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013062617131629-2496132 ; Wed, 26 Jun 2013 17:13:16 +0800 From: Hu Tao To: qemu-devel@nongnu.org Date: Wed, 26 Jun 2013 17:13:32 +0800 Message-Id: <2c8895d39b5503d2665ce648efe1912c1350f845.1372234719.git.hutao@cn.fujitsu.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/06/26 17:13:16, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/06/26 17:13:16, Serialize complete at 2013/06/26 17:13:16 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Cc: Vasilis Liaskovitis Subject: [Qemu-devel] [PATCH v5 09/14] memory controller: initialize dram controller. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Vasilis Liaskovitis Signed-off-by: Hu Tao --- hw/i386/pc.c | 27 +++++++++++++++++++++++++++ include/hw/i386/pc.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 55056b1..65838a6 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1283,6 +1283,27 @@ void mc_set_smm(int val, void *arg) memory_region_transaction_commit(); } +static hwaddr mc_dimm_offset(DeviceState *dev, uint64_t size) +{ + MemoryController *d = MEMORY_CONTROLLER(dev); + MemoryControllerClass *c = MEMORY_CONTROLLER_GET_CLASS(d); + hwaddr ret; + + if (d->below_4g_mem_size + size <= c->pci_hole_start) { + /* if dimm fits before pci hole, append it normally */ + ret = d->below_4g_mem_size; + d->below_4g_mem_size += size; + } else { + /* otherwise place it above 4GB */ + ret = d->above_4g_mem_size + c->pci_hole_end; + d->above_4g_mem_size += size; + } + + d->ram_size += size; + + return ret; +} + static int memory_controller_init(PCIDevice *dev) { MemoryController *m = MEMORY_CONTROLLER(dev); @@ -1353,6 +1374,11 @@ static int memory_controller_init(PCIDevice *dev) PAM_EXPAN_SIZE); } + m->dram_channel0 = dimm_bus_create(OBJECT(m), "membus.0", 8, + c->dimm_offset); + m->pv_dram_channel = dimm_bus_create(OBJECT(m), "membus.pv", 0, + c->dimm_offset); + ram_size = m->ram_size / 8 / 1024 / 1024; if (ram_size > 255) { ram_size = 255; @@ -1388,6 +1414,7 @@ static void memory_controller_class_init(ObjectClass *klass, void *data) dc->no_user = 1; mc->set_smm = mc_set_smm; mc->update = mc_update; + mc->dimm_offset = mc_dimm_offset; } static const TypeInfo memory_controller_type_info = { diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index e2cbc1b..959b92b 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -10,6 +10,7 @@ #include "hw/i386/ioapic.h" #include "hw/pci/pci.h" #include "hw/pci-host/pam.h" +#include "hw/mem-hotplug/dimm.h" #define TYPE_MEMORY_CONTROLLER "memory controller" #define MEMORY_CONTROLLER(obj) OBJECT_CHECK(MemoryController, (obj), TYPE_DEVICE) @@ -29,6 +30,7 @@ typedef struct MemoryControllerClass { void (*set_smm)(int val, void *arg); void (*update)(MemoryController *m); + hwaddr (*dimm_offset)(DeviceState *d, uint64_t size); } MemoryControllerClass; typedef struct MemoryController { @@ -48,6 +50,9 @@ typedef struct MemoryController { MemoryRegion ram_above_4g; hwaddr below_4g_mem_size; hwaddr above_4g_mem_size; + + DimmBus *dram_channel0; + DimmBus *pv_dram_channel; } MemoryController; void mc_update_pam(MemoryController *d);