Message ID | 2ac3cbb3f44c35bf061c0c14a2955a4f8884b30b.1513729519.git.alistair.francis@xilinx.com |
---|---|
State | New |
Headers | show
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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB3377 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.36.82 Subject: [Qemu-devel] [PATCH v4 4/5] xlnx-zcu102: Specify the valid CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: ehabkost@redhat.com, f4bug@amsat.org, alistair.francis@xilinx.com, imammedo@redhat.com, marcel@redhat.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series | Add a valid_cpu_types property | expand |
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index b126cf148b..08b5c28a3a 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -184,6 +184,11 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } +static const char *xlnx_zynqmp_valid_cpus[] = { + ARM_CPU_TYPE_NAME("cortex-a53"), + NULL +}; + static void xlnx_ep108_init(MachineState *machine) { XlnxZCU102 *s = EP108_MACHINE(machine); @@ -216,6 +221,12 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) mc->ignore_memory_transaction_failures = true; mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); + /* The ZynqMP SoC is always a Cortex-A53. We add this here to give + * users a sane error if they specify a different CPU, but we never + * use their CPU choice. + */ + mc->valid_cpu_types = xlnx_zynqmp_valid_cpus; } static const TypeInfo xlnx_ep108_machine_init_typeinfo = { @@ -274,6 +285,12 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) mc->ignore_memory_transaction_failures = true; mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); + /* The ZynqMP SoC is always a Cortex-A53. We add this here to give + * users a sane error if they specify a different CPU, but we never + * use their CPU choice. + */ + mc->valid_cpu_types = xlnx_zynqmp_valid_cpus; } static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {