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Tue, 25 Jun 2024 17:29:29 -0700 From: Nicolin Chen To: , , , , , , CC: , , , , Subject: [PATCH RFCv1 07/10] hw/arm/virt: Bypass iommu for default PCI bus Date: Tue, 25 Jun 2024 17:28:34 -0700 Message-ID: <27c5765e7a945de1c10269f05ca3347b5d62eedb.1719361174.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B075:EE_|IA1PR12MB7541:EE_ X-MS-Office365-Filtering-Correlation-Id: 6453cc0c-adfa-4dab-a3e4-08dc9577111c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: C8onOuZJcVof3n1G/tZBkqCJMvQgpMjjfp7FIQRJ7wGK8HRFqk7eXLE5fPCugKZAC4daPDnX0tIiRqru8pHjyq+WtV5X2DMapd90QreDmIWMErGM+XD1fLA9F4iee9rfddq3ryZoiIPW+FdPWVW4X5xNnzWaOdIBTzs2idYkI+tM7go6QmqRdz9W+cZt9kXsJMwApqAVDCBK632RdPqJtrY7Flxbx+dU2ASjKtj1QuHvdX71FSr/uUkVlAM7Fz0tvuiVnCResHdh8rkoMrCF75j/zhQ2kdXDaApnmS+n8CSPWZOWkKwy9UxH2VFtanoQ8u3yBLjqfmB5VQbwW0NeA4ColQXzOxgPLAYqa3nYDAB4ScckUWtuw0Ow8SY6txCahRtYgPyqN6NXrrIpEKsZNAeNBBtF1W5viKg1aWjhcW9lTiwOCXjUICfjD3xvsgzKlb70Ms83gsWMymuowIKRwgvjkeGqAZYC/Wpd3En0efJ7Qfm+zjTZfZRFsyBJkqrbj74AZAE0rv3dKLL3x5j/NNmWMC6SRI/qSqIHSqOwVmwgGEprJ0VNs9IJCrrPQR+ju67xVlNZkF0dH/w0meX5vONZ44UHClVcXOeO3WUj7y6Mi1AlSJFfgCR4sFTwhxKYIfPS71dfAQ007g3+beZBcBYZEHGEzenk9Mp/4E34IcABT37QelCN7VG32l4kIe7vtaQ53G3f06UQNkqg1NXM1iOuZYdwkI6wJUAGSmnHZgn/tt6M2JskbHJ12yMwutsRIId15H2cP1qt2lJwFpyVdZYhgyebvx0CSlocspzK++T2+6aRTfiEu6lSYH4m/IsJLL1RSafaDBqtP1En/GU4aaaXrqZMxD9Ih8f3yZRNHI4/OWL6ADnCO+pcoNGU6D1byDSyQxj1GYdDikJz5UHwC0AlJYTQb/S84CXeaMiZWofinMiQQ7UiyFj9btUFKpaIGhRlo7fMBbKN9W4BcVMiOeyYlAn1VcrRPDapV5KvgYUh9qEeyhXzrEa/iitleF1V6nzfyqVnKY2gevZyfVJ8QoZD7Oes0ws+9/v5Pn9U5KT4p9TPF+htr9lfCU0K0DCc6ifcfnuqjev0+15dSWmH9YAhsVNpw8uiTQLMlLheEAqaQeMoMm1NwAjQ/c1QcuFu+8zdLYHoC755+ilEVeiB7U4MGa/EQbsJyJjKcFpz4f9HhCRotJ9bircNto2PtwtXW6vBMqzb8HpsyjuhpPIdYNTZ+UrZVbEqchrJPODDv0stsEVn9jl7rQu+Z9WO9mkYdooY0ekGpj95yJ91Ip7S3d5Udv5ox5nFEW8u5x/c9h2l8tye4S//PQ6KdCrGpwgM/uJ62ZiGjfUeVte2LVqP1rf7IBhWx17TtEtws0+pS5SdSIIAqGZRzCjIf0DfHtkI/2DXLr7LpulXKgHUe4xjcQ== X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 00:29:39.8316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6453cc0c-adfa-4dab-a3e4-08dc9577111c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7541 Received-SPF: softfail client-ip=2a01:111:f403:2417::601; envelope-from=nicolinc@nvidia.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, KHOP_HELO_FCRDNS=0.4, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now, all passthrough devices that should benefit from the nested SMMUv3 feature are assigned to dedicated pxb buses. So, the default PCI bus can be only used by emulated devices. In theory, these emualted devices can be still attached to an emualted SMMUv3 instance, yet there is no gain doing that. Set the default PCI bus to bypass iommu, for the maximum performance. Signed-off-by: Nicolin Chen --- hw/arm/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3610f53304..5e91dc8c3d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1708,7 +1708,8 @@ static void create_pcie(VirtMachineState *vms) } pci = PCI_HOST_BRIDGE(dev); - pci->bypass_iommu = vms->default_bus_bypass_iommu; + /* Default bus used by emulated devices does not go through nested SMMUs */ + pci->bypass_iommu = vms->default_bus_bypass_iommu || vms->num_nested_smmus; vms->bus = pci->bus; if (vms->bus) { pci_init_nic_devices(pci->bus, mc->default_nic);