From patchwork Thu Jan 22 01:06:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 431654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 57323140271 for ; Thu, 22 Jan 2015 13:39:13 +1100 (AEDT) Received: from localhost ([::1]:50934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE7fq-0004Im-RS for incoming@patchwork.ozlabs.org; Wed, 21 Jan 2015 21:39:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE7fX-0003yx-DK for qemu-devel@nongnu.org; Wed, 21 Jan 2015 21:38:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YE7fR-0003bd-EB for qemu-devel@nongnu.org; Wed, 21 Jan 2015 21:38:51 -0500 Received: from mail-by2on0076.outbound.protection.outlook.com ([207.46.100.76]:31776 helo=na01-by2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE7fR-0003bQ-3d for qemu-devel@nongnu.org; Wed, 21 Jan 2015 21:38:45 -0500 Received: from BN1BFFO11FD045.protection.gbl (10.58.144.33) by BN1BFFO11HUB037.protection.gbl (10.58.144.184) with Microsoft SMTP Server (TLS) id 15.1.75.11; Thu, 22 Jan 2015 01:06:45 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BN1BFFO11FD045.mail.protection.outlook.com (10.58.145.0) with Microsoft SMTP Server (TLS) id 15.1.59.14 via Frontend Transport; Thu, 22 Jan 2015 01:06:46 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1YE6B7-0004Vp-K3; Wed, 21 Jan 2015 17:03:21 -0800 From: Alistair Francis To: Date: Thu, 22 Jan 2015 11:06:36 +1000 X-Mailer: git-send-email 2.1.1 In-Reply-To: <1d5ae8bcbdadb6495531bf6aa4c510b533e89555.1421885801.git.alistair.francis@xilinx.com> References: <1d5ae8bcbdadb6495531bf6aa4c510b533e89555.1421885801.git.alistair.francis@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-7.5.0.1018-21272.003 X-TM-AS-User-Approved-Sender: Yes;Yes Message-ID: <230cf41b87a440a7a0ea367d61a9ed66@BN1BFFO11FD045.protection.gbl> X-EOPAttributedMessage: 0 Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=alistair.francis@xilinx.com; X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(438002)(199003)(189002)(46102003)(53416004)(110136001)(106466001)(2351001)(86362001)(229853001)(64706001)(33646002)(47776003)(19580395003)(19580405001)(92566002)(74316001)(108616004)(104016003)(48376002)(50466002)(2950100001)(92726002)(50986999)(76176999)(77156002)(87936001)(6806004)(50226001)(42413003)(107986001)(24736002); DIR:OUT; SFP:1101; SCL:1; SRVR:BN1BFFO11HUB037; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; MLV:sfv; PTR:unknown-60-83.xilinx.com; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN1BFFO11HUB037; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:BN1BFFO11HUB037; X-Forefront-PRVS: 0464DBBBC4 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:BN1BFFO11HUB037; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2015 01:06:46.0376 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1BFFO11HUB037 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 207.46.100.76 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v1 2/2] zynq: Update Zynq to init the CPU in the a9mpcore device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch removes the initialisation of the ARM Cortex-A9 in Zynq and instead allows the a9mpcore device to init the CPU. This also updates components that rely on the CPU and GIC, as they are now initialised in a slightly different way Signed-off-by: Alistair Francis --- Changes since RFC: - Rebase hw/arm/xilinx_zynq.c | 70 +++++++++++++++++++------------------------------ 1 files changed, 27 insertions(+), 43 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 06e6e24..88d4473 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -26,6 +26,7 @@ #include "hw/loader.h" #include "hw/ssi.h" #include "qemu/error-report.h" +#include "hw/cpu/a9mpcore.h" #define NUM_SPI_FLASHES 4 #define NUM_QSPI_FLASHES 2 @@ -104,12 +105,10 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, static void zynq_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ObjectClass *cpu_oc; - ARMCPU *cpu; + A9MPPrivState *mpcore; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); @@ -119,39 +118,8 @@ static void zynq_init(MachineState *machine) Error *err = NULL; int n; - if (!cpu_model) { - cpu_model = "cortex-a9"; - } - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); - - /* By default A9 CPUs have EL3 enabled. This board does not - * currently support EL3 so the CPU EL3 property is disabled before - * realization. - */ - if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { - object_property_set_bool(OBJECT(cpu), false, "has_el3", &err); - if (err) { - error_report("%s", error_get_pretty(err)); - exit(1); - } - } - - object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err); - if (err) { - error_report("%s", error_get_pretty(err)); - exit(1); - } - - object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err); - if (err) { - error_report("%s", error_get_pretty(err)); - exit(1); - } - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - if (err) { - error_report("%s", error_get_pretty(err)); + if (machine->cpu_model) { + error_report("Zynq does not support CPU model override!\n"); exit(1); } @@ -186,16 +154,32 @@ static void zynq_init(MachineState *machine) qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); - dev = qdev_create(NULL, "a9mpcore_priv"); - qdev_prop_set_uint32(dev, "num-cpu", 1); - qdev_init_nofail(dev); - busdev = SYS_BUS_DEVICE(dev); + mpcore = A9MPCORE_PRIV(object_new("a9mpcore_priv")); + /* By default A9 CPUs have EL3 enabled. This board does not + * currently support EL3 so the CPU EL3 property is disabled before + * realization. + */ + if (object_property_find(OBJECT(mpcore), "has_el3", NULL)) { + object_property_set_bool(OBJECT(mpcore), false, "has_el3", &err); + if (err) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + } + qdev_prop_set_uint32(DEVICE(mpcore), "num-cpu", 1); + qdev_prop_set_uint32(DEVICE(mpcore), "midr", ZYNQ_BOARD_MIDR); + qdev_prop_set_uint64(DEVICE(mpcore), "reset-cbar", MPCORE_PERIPHBASE); + object_property_set_bool(OBJECT(mpcore), true, "realized", &err); + if (err != NULL) { + error_report("Couldn't realize the Zynq A9MPCore: %s", + error_get_pretty(err)); + exit(1); + } + busdev = SYS_BUS_DEVICE(DEVICE(mpcore)); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); - sysbus_connect_irq(busdev, 0, - qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); for (n = 0; n < 64; n++) { - pic[n] = qdev_get_gpio_in(dev, n); + pic[n] = qdev_get_gpio_in(DEVICE(mpcore), n); } zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);