From patchwork Wed Jun 13 04:46:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 164528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 769F6B6FD1 for ; Wed, 13 Jun 2012 14:38:17 +1000 (EST) Received: from localhost ([::1]:44152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SefLT-0006Mz-62 for incoming@patchwork.ozlabs.org; Wed, 13 Jun 2012 00:38:15 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SefLA-00062Y-Fq for qemu-devel@nongnu.org; Wed, 13 Jun 2012 00:37:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SefL8-0007xV-Ck for qemu-devel@nongnu.org; Wed, 13 Jun 2012 00:37:56 -0400 Received: from mail-pz0-f47.google.com ([209.85.210.47]:56143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SefL8-0007wI-5v for qemu-devel@nongnu.org; Wed, 13 Jun 2012 00:37:54 -0400 Received: by mail-pz0-f47.google.com with SMTP id h21so407584dal.34 for ; Tue, 12 Jun 2012 21:37:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=MHRrL4MnpxaNS45AhYd6Y9fsTLGq8tswpo6+YledlzU=; b=L3X+eWgJU35TgCl7tJQMYHIYfy9RYzxdVdvXfGm0yNCduq6B1Yfb1cTdiRChlD8LPV XR4a/SVXjTBmt1NqPozZ7LN0xi185DO/8Nq3foRwazOCJFkL7JvYqG+MyS5iQa7AAfvA VhAOgUrIjGauUqZyiVAM06xcnIq7u3WkvqTtfLFBphHN6BQbtthK9qCErDRyvHS7Bws/ h+zgCOLQtf3ONYVGti1Z7O445tUPFH53pZQIPLv3o0qyLVomidyvkxdUOpMKkbhPETUj BbfBr8cprjRrxhHTyPHqdm/un0FY/79xVCmZX1zzbLxAbH28pIEqU4kIoNHqeoT6ZJ4F IyCA== Received: by 10.68.236.131 with SMTP id uu3mr3706401pbc.96.1339562273122; Tue, 12 Jun 2012 21:37:53 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id py5sm4393855pbb.1.2012.06.12.21.37.49 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 12 Jun 2012 21:37:52 -0700 (PDT) From: "Peter A. G. Crosthwaite" To: edgar.iglesias@gmail.com, qemu-devel@nongnu.org Date: Wed, 13 Jun 2012 14:46:43 +1000 Message-Id: <20a3c6b94f992c76aafebc7e04449d1753774ffc.1339562634.git.peter.crosthwaite@petalogix.com> X-Mailer: git-send-email 1.7.3.2 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQmwqroj9GHfiqraPuqjPFeWUFzL3lSEqxClsiwfeGR4npiMLzEk1PAESeXW+dtc/iWYb+Iz X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.47 Cc: peter.crosthwaite@petalogix.com, monstr@monstr.eu, john.williams@petalogix.com Subject: [Qemu-devel] [PATCH v2 03/11] xilinx_timer: changed nr_timers to one_timer_only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The configurable property for this IP in the Xilinx tools is a boolean switch "one-timer-only" that flicks this timer from being dual channel to single. Updated QEMU to work the same way for better match with the IP core and its TRM. Signed-off-by: Peter A. G. Crosthwaite --- hw/petalogix_ml605_mmu.c | 2 +- hw/petalogix_s3adsp1800_mmu.c | 2 +- hw/virtex_ml507.c | 2 +- hw/xilinx.h | 4 ++-- hw/xilinx_timer.c | 17 +++++++++++------ 5 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index bff63e3..6a7d0c0 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -123,7 +123,7 @@ petalogix_ml605_init(ram_addr_t ram_size, irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 100 Mhz. */ - xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000); + xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000); /* axi ethernet and dma initialization. TODO: Dynamically connect them. */ { diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 7d83c21..2cf6882 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -106,7 +106,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]); /* 2 timers at irq 2 @ 62 Mhz. */ - xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000); + xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); microblaze_load_kernel(cpu, ddr_base, ram_size, diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index cace86b..79bc0d1 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -229,7 +229,7 @@ static void virtex_init(ram_addr_t ram_size, serial_hds[0], DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 62 Mhz. */ - xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000); + xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000); if (kernel_filename) { uint64_t entry, low, high; diff --git a/hw/xilinx.h b/hw/xilinx.h index 35f35bd..7b8ad51 100644 --- a/hw/xilinx.h +++ b/hw/xilinx.h @@ -16,12 +16,12 @@ xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) /* OPB Timer/Counter. */ static inline DeviceState * -xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq) +xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int oto, int freq) { DeviceState *dev; dev = qdev_create(NULL, "xilinx,timer"); - qdev_prop_set_uint32(dev, "nr-timers", nr); + qdev_prop_set_uint32(dev, "one-timer-only", oto); qdev_prop_set_uint32(dev, "frequency", freq); qdev_init_nofail(dev); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c index e9fde28..72f7c0d 100644 --- a/hw/xilinx_timer.c +++ b/hw/xilinx_timer.c @@ -62,11 +62,16 @@ struct timerblock SysBusDevice busdev; MemoryRegion mmio; qemu_irq irq; - uint32_t nr_timers; + uint8_t one_timer_only; uint32_t freq_hz; struct xlx_timer *timers; }; +static inline unsigned int num_timers(struct timerblock *t) +{ + return 2 - t->one_timer_only; +} + static inline unsigned int timer_from_addr(target_phys_addr_t addr) { /* Timers get a 4x32bit control reg area each. */ @@ -78,7 +83,7 @@ static void timer_update_irq(struct timerblock *t) unsigned int i, irq = 0; uint32_t csr; - for (i = 0; i < t->nr_timers; i++) { + for (i = 0; i < num_timers(t); i++) { csr = t->timers[i].regs[R_TCSR]; irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT); } @@ -202,8 +207,8 @@ static int xilinx_timer_init(SysBusDevice *dev) sysbus_init_irq(dev, &t->irq); /* Init all the ptimers. */ - t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers); - for (i = 0; i < t->nr_timers; i++) { + t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t)); + for (i = 0; i < num_timers(t); i++) { struct xlx_timer *xt = &t->timers[i]; xt->parent = t; @@ -214,14 +219,14 @@ static int xilinx_timer_init(SysBusDevice *dev) } memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer", - R_MAX * 4 * t->nr_timers); + R_MAX * 4 * num_timers(t)); sysbus_init_mmio(dev, &t->mmio); return 0; } static Property xilinx_timer_properties[] = { DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 62 * 1000000), - DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0), + DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0), DEFINE_PROP_END_OF_LIST(), };