| Message ID | 20241222214507.2173648-1-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv/riscv-iommu-sys.c: fix duplicated 'table_size' | expand |
On Mon, Dec 23, 2024 at 7:46 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Trivial fix for the following ticket: > > CID 1568580: Incorrect expression (EVALUATION_ORDER) > In "table_size = table_size = n_vectors * 16U", > "table_size" is written twice with the same value. > > Cc: qemu-trivial@nongnu.org > Cc: Peter Maydell <peter.maydell@linaro.org> > Resolves: Coverity CID 1568580 > Fixes: 01c1caa9d1 ("hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/riscv-iommu-sys.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c > index 28153f38da..65b24fb07d 100644 > --- a/hw/riscv/riscv-iommu-sys.c > +++ b/hw/riscv/riscv-iommu-sys.c > @@ -121,7 +121,7 @@ static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, > uint32_t n_vectors) > { > RISCVIOMMUState *iommu = &s->iommu; > - uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; > + uint32_t table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; > uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; > uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; > uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256; > -- > 2.47.1 > >
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 28153f38da..65b24fb07d 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -121,7 +121,7 @@ static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, uint32_t n_vectors) { RISCVIOMMUState *iommu = &s->iommu; - uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; + uint32_t table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256;
Trivial fix for the following ticket: CID 1568580: Incorrect expression (EVALUATION_ORDER) In "table_size = table_size = n_vectors * 16U", "table_size" is written twice with the same value. Cc: qemu-trivial@nongnu.org Cc: Peter Maydell <peter.maydell@linaro.org> Resolves: Coverity CID 1568580 Fixes: 01c1caa9d1 ("hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/riscv-iommu-sys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)