| Message ID | 20241112091423.2529583-6-fea.wang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Introduce svukte ISA extension | expand |
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote: > > Add "svukte" in the ISA string when svukte extension is enabled. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f219f0c3b5..6d3e9d563d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > > /* These are experimental so mark with 'x-' */ > const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), > DEFINE_PROP_END_OF_LIST(), > }; > > -- > 2.34.1 > >
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote: > > Add "svukte" in the ISA string when svukte extension is enabled. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f219f0c3b5..6d3e9d563d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > > /* These are experimental so mark with 'x-' */ > const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), There should be a check to make sure this isn't enabled for RV32 Alistair
OK, I will add a new commit for checking the extension in RV32. Thank you. Sincerely, Fea On Tue, Nov 19, 2024 at 11:34 AM Alistair Francis <alistair23@gmail.com> wrote: > On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote: > > > > Add "svukte" in the ISA string when svukte extension is enabled. > > > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > > Reviewed-by: Frank Chang <frank.chang@sifive.com> > > Reviewed-by: Jim Shu <jim.shu@sifive.com> > > --- > > target/riscv/cpu.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index f219f0c3b5..6d3e9d563d 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > > + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > > @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig > riscv_cpu_vendor_exts[] = { > > > > /* These are experimental so mark with 'x-' */ > > const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > > + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), > > There should be a check to make sure this isn't enabled for RV32 > > Alistair >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..6d3e9d563d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), DEFINE_PROP_END_OF_LIST(), };