Message ID | 20241112091423.2529583-4-fea.wang@sifive.com |
---|---|
State | New |
Headers | show |
Series | Introduce svukte ISA extension | expand |
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote: > > Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written > value will be masked when the svukte extension is not enabled. > > When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should > do svukte check. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 4b9f899217..fe4e34c64a 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -604,6 +604,7 @@ typedef enum { > #define HSTATUS_VTVM 0x00100000 > #define HSTATUS_VTW 0x00200000 > #define HSTATUS_VTSR 0x00400000 > +#define HSTATUS_HUKTE 0x01000000 > #define HSTATUS_VSXL 0x300000000 > > #define HSTATUS32_WPRI 0xFF8FF87E > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 1936a6f32a..b6fa8ae53f 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, > static RISCVException write_hstatus(CPURISCVState *env, int csrno, > target_ulong val) > { > + if (!env_archcpu(env)->cfg.ext_svukte) { > + val = val & (~HSTATUS_HUKTE); > + } > env->hstatus = val; > if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { > qemu_log_mask(LOG_UNIMP, > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4b9f899217..fe4e34c64a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -604,6 +604,7 @@ typedef enum { #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTW 0x00200000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 #define HSTATUS32_WPRI 0xFF8FF87E diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1936a6f32a..b6fa8ae53f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (!env_archcpu(env)->cfg.ext_svukte) { + val = val & (~HSTATUS_HUKTE); + } env->hstatus = val; if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP,