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[PULL,11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section

Message ID 20241104001900.682660-12-npiggin@gmail.com
State New
Headers show
Series [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() | expand

Commit Message

Nicholas Piggin Nov. 4, 2024, 12:18 a.m. UTC 
From: Philippe Mathieu-Daudé <philmd@linaro.org>

It is unfair to let the PowerNV SPI model to the SSI
maintainers. Also include the PowerNV ones.

Fixes: 29318db133 ("hw/ssi: Add SPI model")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 1e88b5738c..cf39ad4b7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1505,8 +1505,10 @@  F: hw/ppc/pnv*
 F: hw/intc/pnv*
 F: hw/intc/xics_pnv.c
 F: hw/pci-host/pnv*
+F: hw/ssi/pnv_spi.c
 F: include/hw/ppc/pnv*
 F: include/hw/pci-host/pnv*
+F: include/hw/ssi/pnv_spi*
 F: pc-bios/skiboot.lid
 F: tests/qtest/pnv*
 F: tests/functional/test_ppc64_powernv.py