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Tue, 29 Oct 2024 08:19:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGW1QCg7TiuyBlyPBi6p8Zdn9CMlnu+h38IwmZrwi4KsriZB8mPnNJH7WBdwXd8ggdn996epQ== X-Received: by 2002:a05:600c:4e91:b0:431:54f3:11af with SMTP id 5b1f17b1804b1-4319ad2103emr95091325e9.31.1730215142685; Tue, 29 Oct 2024 08:19:02 -0700 (PDT) Received: from [192.168.10.3] ([151.49.226.83]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3c625sm12830442f8f.37.2024.10.29.08.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:19:00 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: tao1.su@linux.intel.com, zhao1.liu@intel.com, xiaoyao.li@intel.com Subject: [PATCH 1/8] target/i386: cpu: set correct supported XCR0 features for TCG Date: Tue, 29 Oct 2024 16:18:51 +0100 Message-ID: <20241029151858.550269-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241029151858.550269-1-pbonzini@redhat.com> References: <20241029151858.550269-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.302, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- target/i386/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5886b44fcf7..f08e9b8f1bc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1318,7 +1318,9 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .needs_ecx = true, .ecx = 0, .reg = R_EAX, }, - .tcg_features = ~0U, + .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | + XSTATE_PKRU_MASK, .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | @@ -1331,7 +1333,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .needs_ecx = true, .ecx = 0, .reg = R_EDX, }, - .tcg_features = ~0U, + .tcg_features = 0U, }, /*Below are MSR exposed features*/ [FEAT_ARCH_CAPABILITIES] = {