diff mbox series

[v1,6/7] target/riscv: Reset SXL and UXL according to sxl32

Message ID 20241007033400.50163-7-zhiwei_liu@linux.alibaba.com
State New
Headers show
Series target/riscv: Support SXL32 on RV64 CPU | expand

Commit Message

LIU Zhiwei Oct. 7, 2024, 3:33 a.m. UTC 
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

When boot a 32-bit system, sxl and uxl should be set to 1 by OpenSBI. However,
OpenSBI does not support this feature.

We temporarily force QEMU reset SXL and UXL to MXL_RV32 when sxl32 is enabled.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
---
 target/riscv/cpu.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index baf8fba467..9dbbb1ca77 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -933,8 +933,17 @@  static void riscv_cpu_reset_hold(Object *obj, ResetType type)
          * The reset status of SXL/UXL is undefined, but mstatus is WARL
          * and we must ensure that the value after init is valid for read.
          */
-        env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
-        env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+        if (cpu->cfg.sxl32) {
+            env->mstatus = set_field(env->mstatus, MSTATUS64_SXL,
+                                      MXL_RV32);
+            env->mstatus = set_field(env->mstatus, MSTATUS64_UXL,
+                                      MXL_RV32);
+        } else {
+            env->mstatus = set_field(env->mstatus, MSTATUS64_SXL,
+                                      env->misa_mxl);
+            env->mstatus = set_field(env->mstatus, MSTATUS64_UXL,
+                                      env->misa_mxl);
+        }
         if (riscv_has_ext(env, RVH)) {
             env->vsstatus = set_field(env->vsstatus,
                                       MSTATUS64_SXL, env->misa_mxl);