diff mbox series

[v1,5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

Message ID 20241007033400.50163-6-zhiwei_liu@linux.alibaba.com
State New
Headers show
Series target/riscv: Support SXL32 on RV64 CPU | expand

Commit Message

LIU Zhiwei Oct. 7, 2024, 3:33 a.m. UTC 
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

Allow reading 32-bit only registers like timeh and stimecmph when
booting a 32-bit Linux kernel on RV64 when sxl32 is true.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
---
 target/riscv/csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 93a5cf87ed..c412ac8e31 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -161,7 +161,7 @@  skip_ext_pmu_check:
 
 static RISCVException ctr32(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_mxl(env) != MXL_RV32) {
+    if (env->xl != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -481,7 +481,7 @@  static RISCVException sstc(CPURISCVState *env, int csrno)
 
 static RISCVException sstc_32(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_mxl(env) != MXL_RV32) {
+    if (env->xl != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }