From patchwork Mon Oct 7 03:33:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1993349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=H3Nnf3k6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XMPtR2cyfz1xtV for ; Mon, 7 Oct 2024 14:35:25 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sxeWR-0005J1-SZ; Sun, 06 Oct 2024 23:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWP-0005Im-So; Sun, 06 Oct 2024 23:34:57 -0400 Received: from out30-97.freemail.mail.aliyun.com ([115.124.30.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sxeWM-00064w-VJ; Sun, 06 Oct 2024 23:34:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1728272090; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=QFlizzQXd2Vzk0KL2AZvVmfiBZ91I9MAYtLOcFJEyXA=; b=H3Nnf3k6u9vD4HKXcHaNtIekmBka9aktT/KK+j0tA47QEnI+XnseZ+qPsvSGAjLMKIHwuuGYaSGQA8rNMnXi1mHoe8wsRpKI0373RaL+4yQNq3Za/Z/6AV+luLRbfKOYnBUUlSFZyoMgH7a6rSlJ6m1Tj0V2oqJgZunIvi6f2Wc= Received: from localhost.localdomain(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WGLRZQe_1728272088) by smtp.aliyun-inc.com; Mon, 07 Oct 2024 11:34:49 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Subject: [PATCH v1 1/7] target/riscv: Fix sstatus read and write Date: Mon, 7 Oct 2024 11:33:54 +0800 Message-Id: <20241007033400.50163-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> References: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.97; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-97.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: TANG Tiancheng Sstatus is SXLEN bits in length and always has the layout determined by the SXL configuration, regardless of the current XLEN. Signed-off-by: TANG Tiancheng Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand) Fixes: f310df58bd (target/riscv: Enable uxl field write) --- target/riscv/csr.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea3560342c..b33cc1ec23 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2893,7 +2893,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, { uint64_t mask = sstatus_v1_10_mask; uint64_t sstatus = env->mstatus & mask; - if (env->xl != MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } @@ -2905,11 +2905,10 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask = (sstatus_v1_10_mask); - if (env->xl != MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } - /* TODO: Use SXL not MXL. */ - *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); + *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } @@ -2918,7 +2917,7 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (env->xl != MXL_RV32 || env->debugger) { + if (riscv_cpu_sxl(env) != MXL_RV32 || env->debugger) { if ((val & SSTATUS64_UXL) != 0) { mask |= SSTATUS64_UXL; }